DWC ADC 12b5M SAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 23-30
10Application Notes
Cell Placement
In addition to employing all known design techniques that reduce the sensitivity to digital
switching noise, the SAR ADC is surrounded by shielding guardrings, connected to the p-
substrate and to an N-well.
To improve noise isolation, the SAR ADC should be as close possible to the analog pads,
and lie in the quietest place in terms of digital activity. This is achieved by increasing, as
much as possible, the distance between the SAR ADC core and:
1. The most active/noisy digital output pads/pins.
2. The most active/noisy digital core area.
3. The most active/noisy digital input pads.
If the region between the SAR ADC and the noise generating circuits is empty, one can add
a N-well guard area with PMOS devices inside, to be used as additional decoupling
capacitors for the analog supply.
Increasing the distance between the SAR ADC and the digital circuits produces better
results with high resistive substrates. The maximum noise isolation is accomplished utilizing
the Deep Nwell option.
Any modification on the metal layers within the ADC area, resulting either from metal filling
or by routing at chip level, can result in a serious degradation of its performance. For this
reason the ADC complies with the metal density DRC rules thus requiring no further metal
filling, and includes metal exclusion layers to indicate that no routing should be made on top
of it. Furthermore, at chip level, any signals unrelated to the ADC should be routed at a
distance not lower than 20um, to avoid any signal coupling through parasitic capacitances.
Power Supplies
Use dedicated supply Pins and Pads for the SAR ADC. If this is not possible, then:
1. In case of a Pin limited ASIC, share power supply pins with other cells by employing
double bonding (2 pads connect to 1 pin).
2. In case of a Pad limited ASIC, share power supply Pads by merging the supply lines of
different cells as close as possible to the Pad.
There must always be different IO Pad rings for analog and digital cores.
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