TB9100 Reciter Service Manual Network Circuitry 49
© Tait Electronics Limited January 2006
In the event that a bus cycle is not successfully completed, either the retry
(RETRY
) signal can be asserted to re-run the bus cycle, or the transfer error
acknowledge (TEA
) signal can be asserted to cancel the bus cycle. Since
neither of these signals is used in the ASIF, there exists a possibility that the
MPC will wait forever for a bus cycle to complete. To catch any such
occurrences, the bus monitor (see “Time Bases and Watchdog” on page 42)
terminates excessively long bus cycles.
Normal bus operations initiated by the MPC are synchronous to the
memory clock, CLKOUT, ie. all control outputs are timed from the rising
edge of the clock. Similarly, all control inputs must be set up at a suitable
time, prior to the rising edge of CLKOUT, to be recognized during the next
clock cycle.
Memory Controllers The MPC implements a glueless interface to standard memory types and
peripherals through three programmable memory access controllers; the
General-purpose Chip Select Machine (GPCM) and the User-
Programmable Machines (UPMA and UPMB). UPMA and UPMB are
architecturally identical. A full description of the operation of these memory
controllers is beyond the scope of this document; chapter 15 of the MPC866
user’s manual (reference 2) should be consulted for full details.
Between them, these controllers can generate the necessary control signals
to interface with parallel bus devices such as:
Figure 5.4 MPC External Bus Cycle Sequence
TSIZ[0-1], AT[0-3]
CLKOUT
A[0-31]
R/W
BURST
TS
Data
TA
Data is sampled
To Next Page
Loading...
Need help?
General
