Tektronix 2235 User Manual

T heory of Operation-2235 Service
delay time (Runs After Delay) or upon receipt of the first

tentiometer R6440
.
The
output of the comparator is used to
trigger signal
after the delay time h as elapsed . This delay

initiate
α
Β
Sweep a nd to control the ΒΖ -Axis L ogic circuit
time is α f unction
of the Β Delay Time P osition Com p arator

switching .
circuit and the Α sweep .
The
inputs to the comparator, U 655, are the wiper volt-
Β M iller
Sweep Generator

age of
R
9644 and the Α Sweep voltage from the d ivider
T
he Β M iller Sweep Generator is composed of 0709,

network composed of R 651, R 652, and R 653 . Input voltage
ranges to the
com
p
arator are determined by VR645 and
0710
Α ,
0710
Β , Q712,
and associated timing components .

R
646 for the noninverting input
and by
R
652 for the invert-
This circuit
produces the Β Sweep and f unctions in the

ing
input . Delay Start potentiometer R646 is adjusted in
same manner as the Α M iller Sweep Generator ; see the

conjunction with
potentiometer R 652 to set the ΒD ELAY
" Α M iller
Sweep Generator" section for α description of cir-

TIME
P OSITION
dial calibration
.
cuitry
operation
. The
output at the collector of 0712 drives
the H orizontal Amplifier
and Q643 .
Β Trigger L evel Comparator
T
he
ΒT rigger
L evel Comparator is composed of transis-
tor array U
605, U 625C, Q619, and Q620 . This circuit deter-
mines
both
t
he trigger level and slope at which t he
Β triggering signal
is p roduced . It functions in the same
manner as the Α Trigger L
evel Comparator with t he exclu-
sion of the TV Trigger
and Trigger V iew circuitry . See the " Α
Trigger L evel Comparator" section for α d escription of the
circuit
operation
.
Buffering of the inverting and noninverting
outputs
of U 625D is p rovided b y U 625A and U 625B, and
Q630 and 0631
level
shift the signals to TTL levels . The
circuit output at the collector
of Q630 sup plies trigger sig-
nals to clock U670A .
Runs After
Delay
T
he
R
uns
After
Delay circuit allows the Β Sweep Logic to
generate α Β
Sweep independently of any Β Trigger signals .
In
the R uns After Delay
mode,
ΒT
RIGGER LEVEL control
R 602 is rotate d fully clockwise . This
b iases off 0637 and
p laces
α
L O
on the collector
.
Inverter U 660D will then h ave
α HI output with resistor R
640
providing p
ositive feedback .
The output of U 660A will
therefore b e
L
O and U670A will b e
h eld set with t he
Q
output L
O .
If the ΒTRIGGER LEVEL
control is not fully clockwise,
0637 is b iase d on and t
he
Β
Sweep is in t he triggered
mode . The output of U
660D
will
b e
L
O, the output of U 660A
will b e
HI,
and U670A will
no
longer
b e h eld set .
Operation of the Β Sweep L ogic circuitry under both
of
these conditions is d escribed in t he " Β Sweep Logic"
d iscussion .
Β
Delay
Time P
osition Comparator
T
he
Β
Delay
Time P
osition Comparator circuit compares
the amplitude of the Α Sweep sawtooth o utput voltage to
the
do voltage
level
set by ΒD ELAYTIME P OSITION ρο -
3- 1
2
The
out
p
ut of the comparator is enabled o r d isab led by
the strobe signal connected to p in 6 . Whe n the Α Only signal
is
HI,
the
comparator is enabled . When Α Only is LO, the
output of the
comparator is α h igh impedanceand t herefore
α
HI
is p
resent on
p in
9 of U 680C .
Β
Swee p
L
ogic
T he Β Swee p L ogic circuitry utilizes signals from the as-
sociated Β Swee p circuitry to generate control signals for
both
t
he
Β M
iller Swee p and the Β Ζ -Axis Switching L ogic
circuits .
In the R uns After Delay mode, U 660A p laces α L O on the
S input of U 670A . During the p revious h oldoff p eriod,
U 680D p in 13 strobed L O . The output of the flip-flop com-
p osed of U 680C and U 680D went Hl and the output of
U 660F went L O . W ith both t he S and R i nputs of U 670A
L O, the 0 output is HI to bias on 0709 and prevent the
Β M iller Sweep from running . Once the Α Sweep voltage at
U 655 pin 3 exceeds the voltage at pin 2, the comparator
out p ut will go L O . The flip-flop composed of U 680C and
U680D will change out p ut states and cause the R i nput of
_U670A to be HI . The L O on the S in p ut will then cause the
0 output of U 670A to go L O . This will shut off Q709 and the
Β M iller Sweep Generator will p roduce α linear ramp . If the
ramp voltage reaches about 12 V, sweep-end comparator
0643 will turn on and cause the output of U 665D to go HI .
The
Β M iller Sweep Generator will continu e to run, but the
trace
will
b e b lanked because the Β Gate line is HI which
reverse b iases CR817 . Once the ramp is at approximately
13 V, VR712 will conduct and prevent the voltage from in-
creasing further .
The Β Sweep Generator will be
reset for another sweep
by one of two means . If the Α Sweep doesn't end
before
the
Β Sweep, the
Generator
will not
be
r
eset
until
the Alt Sync
line goes from HI to L O to change the U
680C-U680D
flip-flip
output states . The R input of U 670A will then be L
O, caus-
ing the ( λ output to be HI and r eset the Generator . Depend-
ing on the settings of the Α and Β S EC/DIV switches, the Α
Sweep may end b efore the Β Sweep . If this occurs, the Alt

Tektronix 2235 Specifications

General

Bandwidth	100 MHz
Channels	2
Vertical Sensitivity	2 mV/div to 5 V/div
Maximum Input Voltage	400 V (DC + AC peak)
Rise Time	3.5 ns
Vertical Resolution	8 bit
Input Impedance	1 MΩ || 20 pF
Power Requirements	90 to 250 V AC, 48 to 440 Hz
Trigger Modes	Auto, Normal, Single
Display	CRT
Weight	17 lb (7.7 kg)