Maintenance—2465B/2467B Service
By holding one of the momentary switches in a closed
position when power is first applied, this test will
fail,
and
the Diagnostic Monitor will be entered. When the test is
started from the Diagnostic Monitor, a one-half second
delay is incorporated to allow the COUPLING (test start)
switch to return to its normal (open) position. Table 6-4,
above,
defines the error codes that may be encountered
when a switch is detected as closed.
NOTE
When the user presses the lower TRIGGER COU-
PLING switch to stop this
test,
an error code may be
generated. This is normal and does not indicate an
actual failure.
Test checks: Momentary switches, row scanning
circuitry, and column scanning circuitry.
READOUT BOARD (Test 03). This two-part test checks
the interface to the Readout Board from the
Microprocessor and the character RAM circuits.
Processor Interface Test—The Microprocessor loads
the three, eight-bit shift registers with an alternating bit
pattern that is then shifted back to the processor for
comparison.
Test checks: Data Registers, data strobes (clocks),
and the data input and output lines.
RAM Test—A
"1"
is rotated through each byte of the
Readout RAM, one bit at a time. Each time an additional
bit is rotated into the byte, the byte is loaded into the
processor interface and clocked back to the processor for
comparison. The byte is then restored to its original
content, and each successive byte is tested in the same
manner.
Test checks: Readout RAM addressing, Readout RAM
data lines, and RAM read/write capability.
CALIBRATION DATA (Test 04). Three checks are
performed on the RAM to verify its contents.
Checksum Test—The contents of locations containing
calibration constants are checksummed using a spiral-add
technique. The result is compared to the stored checksum
generated at the time of calibration.
Test checks: RAM addressing and RAM contents.
Parity Test—As each of the calibration constants is
read for the Checksum test above, the parity of each 14-
bit word is checked.
Test checks: CALIBRATION DATA integrity and RAM
CALIBRATION DATA retention.
Limit Test—Checks for valid calibration data.
Test checks: The contents of locations containing
calibration data are compared to their stored limits.
MAIN BOARD (Test 05). The AUTO LVL triggering
feature (a routine stored in firmware) is operated to detect
the peaks of a Line Trigger signal. Detected peaks are
compared to expected values to verify operation (and
calibration) of interrelated signal processing circuits.
Test checks: Line Trigger source, the A Trigger
generation circuitry, and Control DAC U2101 (located on
the Control board, diagram 2).
BATTERY VOLTS (Test 06). The battery voltage is
read and compared to stored constants. If the voltage is
above or below the stored limits the appropriate error code
is displayed.
Test checks: Battery voltage, voltage follower
operational amplifier U2620C, and CR2770.
Exerciser Routines
The Exerciser routines (see Table 6-5, above) allow the
operator to set and examine various bytes of control data
used in determining instrument function.
POTS AND SWITCHES (Exerciser 01). This routine
displays the values that the Microprocessor detects as the
various digitized pots and switches are activated. The left
half of the top line of the display appears after turning a
pot. The right half of the top line of the CRT display
appears after pressing a switch. The top line of the CRT
display has the following format:
AA BB CC DEEE FF GG HI JJ KL
The format is defined as follows:
"AA" is the code of the most-recently-activated
potentiometer (see Table 6-9 for definition of pot codes).
6-15
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