Theory of Operation—2465B/2467B Service
the BLANK control signal is driven by the readout blank
( ROB ) input signal on pin 5 (also from the Readout
circuitry). The readout active line ( ROA , pin 6), when set
LO,
tells the Readout circuitry that readout dots may be
displayed if necessary. The ROA signal is always set LO
at the start of the trigger holdoff time following sweeps,
and it is held there until the holdoff time is almost over.
This allows the majority of holdoff time to be used for
displaying readout dots. The Display Sequencer will switch
the ROA signal back to HI before the end of holdoff so
that the readout display does not interfere with display of
the vertical signal at the triggering event.
TRACE SEPARATION. Vertical separation between the
A Sweep trace and the B Sweep traces (for alternate
horizontal sweep displays), and between the reference B
Sweep trace and the delta B Sweep trace (when delta
time is selected in B Sweep only mode), is enabled by the
TS1 +TS2 output.
X10 HORIZONTAL MAGNIFICATION. Horizontal X10
magnification is controlled by the MAG output.
CALIBRATOR TIMING. The 5-Hz to 5-MHz drive signal
to the Calibrator circuitry is provided by the CT output.
DELAY GATE OPERATION. Analog Switches U850B
and U850C select the delay references for each sweep.
Depending on the display mode and point in the display
sequence, the DS control signal (U650 pin 40) routes one
of the two analog delay references through U850B and
U850C to the two sweep hybrids. The selected reference
level is compared against the changing sweep ramp
voltages to generate the delay gates that control each
sweep's functions.
After an A Sweep has been initiated by a trigger, a
delay gate circuit within U700 compares the A Sweep
ramp voltage to the selected delay reference. When the
sweep ramp reaches the delay reference level, the DG
(delay gate) output goes LO, enabling the B trigger portion
of U500 and B Sweep hybrid U900. Then, when B trigger-
ing occurs (for TRIG AFT DLY mode), the A/B Trigger
hybrid sets the TGB (trigger gate B) signal LO, initiating
the B Sweep. In RUN AFT DLY mode, however, the TGB
signal to U900 is held LO, and the B Sweep is initiated at
the end of the A Sweep delay time when the A Sweep
delay gate goes LO.
STATUS MONITORING. As the Display Sequencer
controls the display system in real time, it continually
monitors the trigger and sweep operations and updates
the internal trigger status register accordingly. The
Microprocessor checks the contents of this register every
3.3 ms to determine the current status of the trigger and
sweep circuitry. The Microprocessor reads the trigger
status register by generating a series of trigger status
strobe ( TSS ) pulses (U650 pin 19) to serially clock the
contents of the register out to the TSO (trigger status
output) line and onto the Data Bus (via Status Buffer
U2220 on diagram 2). The system status information
obtained by this check is used for AUTO LVL triggering,
AUTO free-run triggering, detecting the completion of all
sweeps in a SGL SEQ display, automatic measurement
functions, and during instrument calibration.
INTENSITY CONTROL. The Display Sequencer controls
the intensity for both sweep and readout displays. The
analog levels at pins 22 and 23 determine the basic
intensity level of the displays. Two internally generated
DAC currents (developed by multiplying the IREF current
at pin 20 by two processor-generated numbers stored
internally) are added to the basic intensity level currents to
produce the display intensity seen on the crt (see Table 3-
1).
The two DAC currents added to the INTENSITY
current are dependent on sweep speed, number of
channels being displayed, and whether or not the X10
MAG feature is in use. These added currents increase crt
beam current and hold the display intensity somewhat
constant under the varying display conditions. The
resulting current is applied to Z-Axis Amplifier U950
(diagram 6) from the BRIGHT output of the Display
Sequencer (pin 21).
To produce the intensified zone on the A Sweep trace
for A intensified by B Sweep displays, an additional
current is added to the crt drive signal by the Z-Axis
Amplifier during the concurrence of the SGAZ and SGBZ
(sweep gate A and B z-axis) signals.
The readout intensity (ROI) level, controlled from the
front-panel READOUT INTENSITY pot (via MUX U2530
and sample-and-hold U2630A and C2732). The Micropro-
cessor increases readout intensity when the pot is rotated
either direction from center. Minimum readout intensity
current occurs at the midpoint of the READOUT INTEN-
SITY pot rotation. The Microprocessor also detects to
which side of center the READOUT INTENSITY control is
set. Depending on the status received, the processor sets
up the Readout circuitry (diagram 7) to display either all of
the readout information or just the "delta type" readouts.
Blanking of the crt display during CHOP VERTICAL
MODE displays or when switching between dot positions
in the readout displays is controlled by the Display
Sequencer's BLANK output (pin 3). When the signal is LO,
the crt z-axis is turned on to the selected intensity level;
when HI, the crt display is blanked.
3a-18
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