Theory
of
Operation—2465B/2467B Service
10
MHz
REFRESH
(625
KHz)
ROSFRAME
U2850A-5
U2850B-9 (SI
)
(INCREMENT
ENABLE)
U2850B-8
SETS
PRIORITIZER
TO INCREMENT
INCREMENTS
PRIORITIZER
'"NOTE-IF
S0 IS
ALSO
HI AT
THIS TIME,
THE
PRIORITY DOES
NOT
CHANGE.
3831-06
Figure 3-8. Timing of Refresh Prioritizer.
The next REFRESH clock increments the display prior-
ity to one by clocking a HI to the Q
D
output (pin 12) of
prioritizer shift register U2985. (Table 3-7 illustrates the
operation of U2985.) The same clock latches the now LO
ROSFRAME request at U2850B pin 12 to the Q output
(pin 9), where it is applied to the S1 input (pin 10) of priori-
tizer U2985. The LO on the S1 input of the prioritizer will
remain until another ROSFRAME request from the Timing
Logic occurs, and the encoded priority at the output pins
of U2985 will remain as it is presently set.
As each of the consecutive dots of the readout frame
are displayed, the Dot and Character Counters increment
until all dots of the subframe have been displayed (eight
characters). As the Character Counter increments to
address the next character of the display (first character of
the next frame), the fourth bit of counter U2940 goes HI
and sets the SO input (pin 9) of prioritizer U2985 HI via
exclusive-OR-gate U2990A. The Dot Timer then clocks the
prioritizer with a REFRESH clock on pin 11 of U2985, and
the priority is decremented back to zero (indicating that
the subframe is completed). The next ROSFRAME request
starts the process over again to display the next subframe
of readout display. The sequence just described is the
priority one display mode and is used when holdoff time
between sweeps allows all dots of the subframe to be
displayed before the next ROSFRAME request occurs.
If a second ROSFRAME request occurs before the
Character Counter indicates the end of the subframe (to
decrement the prioritizer back to zero), input S1 of U2985
will be set HI (while the SO input pin remains LO) and the
Prioritizer will increment to priority two (outputs Q
c
and
Q
D
go HI) on the next STARTDOT cycle. If this display
priority still is inadequate to complete the subframe display
before the next ROSFRAME request occurs, priority two
will be incremented up to priority three, or even to priority
four should the condition persist. Priority four is operation-
ally the same as priority three, but it is used to keep the
readout circuitry continuously displaying readout data on
through the next subframe, thus allowing the display to
catch up. If priority four is in effect, the next decrement
that occurs at the end of a subframe only returns the
prioritizer to priority three, not to priority two.
The circuit composed of flip-flop U2950B and
exclusive-OR-gate U2990A enables either edge of the CA3
bit to decrement the priority of the display when a sub-
frame is completed. Either a negative or positive transition
on pin 2 of U2990A will cause the output at pin 3 go HI
since the Q output of U2950B is still at the opposite level.
The HI from U2990A indicates that the end of the present
subframe has occurred, and it sets up the prioritizer to
decrement with the next REFRESH clock. At the same
time that the prioritizer decrements, the changed level of
the CA3 bit is clocked through U2950B and causes the
output of exclusive-OR-gate U2990A to return LO until the
next subframe is completed.
3a-33
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