Theory of Operation—2465B/2467B Service
If the subframe is completed (SO on U2985 goes HI)
when a ROSFRAME request is also pending (S1 is also
HI),
U2985 does a parallel
load,
reloading the present
priority back into the prioritizer. Since, in this case, the
subframe display was completed at the same rate as the
ROSFRAME request occurred, the readout display priority
is not changed.
Dot Start Governor
The Dot Start Governor detects the display priority
from the Refresh Prioritizer and initiates dot-display cycles
as the appropriate conditions are met. The conditions
tested include display priority, sweep gate completion, dot
completion, readout control status, and the readout active
enable from the Display Sequencer.
When the readout board status line (ACTIVE/
ADDRESSABLE ) is HI (signifying display) and the REST
line goes HI to indicate that the dot cycle is complete,
NAND-gates U2890C and D generates a HI at pin 11
(DOTOK) to signal that a new dot display is allowed. The
HI from U2890C and D enables most of the gating in the
Dot Start Governor. If the Refresh Prioritizer has encoded
a display priority of either one or two, the output of
exclusive-OR-gate U2990B is HI. When DOTOK from
U2890C and D goes HI to enable a dot display, the LO
reset from pin 8 of U2970C and D to pin 1 of flip-flop
U2880 is removed. Now, when the A Sweep gate ( SGA )
goes HI (beginning of Holdoff), the HI at the_D input of
U2880B is clocked to the Q output and the Q output at
pin 8 will go LO, requesting display of a priority one or two
dot. This LO dot request is propagated through U2885C,
U2965C and D, and U2890B and sets the STARTDOT
sig-
nal LO. STARTDOT going LO resets Dot Cycle Generator
shift register U2995 and counter U2830B of the Dot Timer.
Resetting the Dot Cycle Generator shift register causes
the REST signal from U2995 pin 13 to go to a LO, remov-
ing the HI DOTOK signal at U2890 pin 11. As DOTOK
goes LO, STARTDOT at pin 8 of U2890B goes HI to start
the DOT Cycle Generator. At the same time the reset to
U2880B is asserted via U2970C and D and the dot
request is removed. Both the Dot Timer and the Dot Cycle
Generator are now enabled and start the first dot-display
cycle during holdoff time.
After the Display Sequencer U650 (diagram 5) has time
to respond to the end of the sweep gate, it sets the
readout active signal ( ROA ) to pin 10 of U2880B LO.
This sets pin 9 of U2885C LO, and the signal is pro-
pagated through U2885C, U2965C and D, and U2890B, as
before, resetting the Dot Timer and the Dot Cycle Genera-
tor. REST then goes LO as before and starts the Dot
Cycle Generator and Dot Timer. This cycle continues,
displaying one dot per cycle (except for the first non-
displayed dot of a character which is automatically initiated
by EOCH2 , until the Display Sequencer determines that
the readout time is over (sets ROA HI) or until the display
priority is decremented to zero.
When a display priority of three or four exists, the out-
put of U2990B will be LO, and U2970C and D, U2880B,
and the associated logic gates following it will not be able
to initiate a dot cycle. In either of these display priorities,
U2970A and B, U2835C, U2965A and B, and flip-flop
U2950A detect the higher priority and generate a readout
request signal ( ROR ) to the Display Sequencer. The LO
from U2950A pin 6 propagates through U2965C and
U2890B to initiate a STARTDOT cycle. When the Display
Sequencer recognizes that the readout request signal is
LO,
it will perform the mode-dependent setup functions
necessary to give display control to the Readout Board
and will then set the ROA (readout active) line LO. The LO
will be clocked into U2880B, and the Dot Cycle Generator
will generate a GETDOT signal, resetting the readout
request from flip-flop U2950B. Only one dot is displayed
for each readout request.
A similar readout display request will be generated
when priority-two-or-higher displays are required when
sweep gates are not present (dot display during triggerable
time after holdoff). This condition is detected by NAND-
gate U2885A. NAND-gates U2970A and B allows a
readout request to be generated when in the interfere
mode This mode is always invoked in 2467 B instruments
and invoked only during a single-sequence waveform
display in 2465B instruments and ensures that all of the
selected sweep combinations are displayed once, followed
by a complete readout frame (for the purpose of crt pho-
tography).
Dot Cycle Generator
The Dot Cycle Generator, composed of shift register
U2995, flip-flop U2880A, and associated gating circuitry,
generates time-related signals for the following purposes:
unblanking the crt to display a dot; requesting the next
byte of dot data in preparation for displaying the next dot;
and reenabling itself to repeat the tasks, via the Dot Start
Governor (dependent on the display priority).
The timing relationships of the Dot Cycle Generator
output signals are controlled by shift register U2995. When
the Dot Start Governor initiates a STARTDOT cycle as
previously described, the STARTDOT signal initially goes
LO,
resetting all the Q outputs of U2995 LO and setting
the Q output of flip-flop U2880A to a HI. The STARTDOT
signal is then returned HI, and the Dot Timer counter
U2830 and shift register U2995 are enabled. The shift
register begins to consecutively shift HI logic levels to its Q
output pins with each 5-MHz clock from the Dot Timer.
After approximately 400 ns, pin 5 (Q
c
) of the shift register
will go HI. The HI at Q
c
propagates through exclusive-
OR-gate U2990D and NAND-gates U2980A and D to
unblank the crt by setting the readout blanking signal (
ROB ) HI.
3a-34
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