Theory of Operation—2465B/2467B Service
When the Q
F
output of U2995 goes HI (1 /is after
STARTDOT), the output of U2990D goes LO and the out-
put of U2990C goes HI. The LO from U2990D propagates
through U2980A and D to blank the crt ( ROB goes LO)
and to clock flip-flop U2880A via NAND-gate U2980B. The
ROA (readout active) level from the Display Sequencer
(diagram 5) is clocked from the D input (pin 2) of U2880A
to the Q output; and, if LO (indicating that the readout cir-
cuitry had control of the crt when unblanking occurred;
thus the dot was displayed), the output of U2980C is set
HI.
With three HI levels applied to NAND-gate U2885A, a
GETDOT request is generated to get the next byte of dot-
position data for display. The next 5-MHz clock sets the
Q
G
output of U2995 HI, and the output of U2990C goes
LO,
removing the LO GETDOT signal.
At 1.4 ^s after STARTDOT goes HI, U2995 pin 13 (Q
H
)
goes HI to produce the REST signal, indicating that the
current dot cycle is complete and the Dot Cycle Generator
is at REST. If the readout ACTIVE/ ADDRESSABLE mode
bit at U2980C pin 10 is still HI, the REST signal going HI
produces a HI DOTOK signal (next dot is allowed) at pin
11 of U2890D. This HI applied to pin 4 of U2890B, along
with any of the possible dot requests from the Dot Start
Governor, will initiate another STARTDOT cycle for the
next dot of the display. As long as the Display Sequencer
holds the readout active line ( ROA ) LO, U2885B, U2965C
and D of the Dot Start Governor will automatically initiate
dot cycles as soon as the previous one ends (REST goes
HI),
until the Refresh Prioritizer is decremented to zero.
When the last dot of the character is called from the
Character ROM, the EOCH bit (DD7) applied to latch
U2905 at pin 18 (in the Vertical Character DAC circuitry) is
LO.
At the end of that dot display cycle, the GETDOT
sig-
nal (going HI) clocks the LO EOCH bit into latch U2905
and increments character counter U2940. The latched bit
becomes the EOCH1 signal (end of character, delayed one
dot request) and is applied to U2855A, along with the
already LO EOCH bit, to reset Dot Counter U2870. The
least-significant bits to the Character ROM address pins
(A0 through A4) are then zeros, and the first dot of the
next character is addressed. The Horizontal and Vertical
DACs don't write this first dot position data into their
registers until the end of the next GETDOT signal. That
same GETDOT signal also clocks EOCH1 into U2905
which becomes EOCH2 at pin 16 (end of character,
delayed by two dot requests). EOCH2 is applied to
NAND-gate U2980D and disables the gate prior to the
time the Dot Cycle Generator attempts to unblank the crt
for the first dot display; thus the first dot of a character is
never displayed.
Disabling the unblanking path for the first dot of each
character in the manner just described allows the more
radical voltage changes between characters to settle
before the actual display of the next character begins.
When the dot data for one of these undisplayed dots also
has the EOCH bit set LO, it is a space character, and the
display is advanced to the next character.
Dot Timer
The Dot Timer, composed of U2890A and U2830,
gen-
erates three, time-related signals used to synchronize the
display and maintain the proper sequencing of the
indi-
vidual character dots.
The two least-significant bits of the Dot Timer, from
U2830 pins 11 and 10, are reset at the beginning of a dot
cycle by a LO STARTDOT signal applied to the reset input
of the counter via U2890A. As the dot-display cycle
begins, the STARTDOT signal returns HI and the Dot
Timer begins counting in a binary fashion. The 10-MHz
clock applied to pin 13 is divided by two to produce the 5-
MHz clocking signal at output pin 11. The 5-MHz clock
sequences the Dot Cycle Generator through the various
phases of the dot-display cycle. The REFRESH output
sig-
nal from U2830 pin 4 updates the Refresh Prioritizer as
each subframe is displayed.
A third clock, from U2830 pin 6, occurs at approxi-
mately
8-MS
intervals and allows any pending dot requests
to generate a ROR signal to the Display Sequencer via
flip-flop U2950B. (Readout request generation is described
in the Dot Start Governor discussion.)
HIGH VOLTAGE POWER SUPPLY AND
CRT FOR 2465B ONLY
The High-Voltage Supply and CRT circuit (diagram 8)
provides the voltage levels and control circuitry for opera-
tion of the cathode-ray tube (crt). The circuitry consists of
the High Voltage Oscillator, the High Voltage Regulator,
the Cathode Supply, the Anode Multiplier, the DC Re-
storer, Focus Amplifiers, the CRT and the various CRT
Control circuits.
High-Voltage Oscillator
The High-Voltage Oscillator transforms power obtained
from the -15 volt unregulated supply to the various ac
levels necessary for the operation of the crt circuitry. The
circuit consists of transformer T1970, switching transistor
Q1981,
and associated circuitry. The low-voltage oscilla-
tions set up in the primary winding of T1970 are raised by
transformer action to high-voltage levels in the secondary
windings. These ac secondary voltages are applied to the
DC Restorer, the Cathode Supply, and the anode multi-
plier circuits.
Oscillation occurs due to the positive feedback from the
primary winding (pin 4 to pin 5) to the smaller base-drive
winding (pin 3 to pin 6) for transistor
Q1981.
The
fre-
quency of oscillation is about 50 kHz, and is determined
primarily by the resonant frequency of the transformer.
3a-35
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