Theory of Operation—2465B/2467B Service
Most of the activities of the instrument are directed by
a microprocessor. The microprocessor, under firmware
control (firmware is the programmed instructions contained
in read-only memory that tells the processor how to
operate), monitors instrument functions and sets up the
operating modes according to the instructions received.
Various types of data read to and from the Micropro-
cessor (program instructions, constants, control data, etc.)
are all transferred over a group of eight bidirectional signal
lines called the Data Bus. The Data Bus is dedicated
solely to microprocessor-related data transfer.
Another group of signal lines, called the Address Bus,
are responsible for selecting or "addressing" the memory
location or device that the Microprocessor wants to com-
municate
with.
Typically, depending on the instruction
being executed, the processor places an address on the
Address Bus to identify the location the Microprocessor
must communicate
with.
This address, along with some
enabling logic, opens up an appropriate data path between
the processor and the device or memory location via the
Data Bus; and data is either read from or written to that
location by the processor.
While executing the control program, the Microproces-
sor retrieves previously stored calibration constants and
front-panel settings and, as necessary places program-
generated data in temporary storage for later use. The
battery backed up RAM provides these storage functions.
When power is applied to the instrument, a brief initiali-
zation sequence is performed, and then the processor
begins scanning the front-panel controls. The switch set-
tings detected and the retrieved front-panel data from the
battery backed up RAM causes the processor to set
vari-
ous control registers and control voltages within the instru-
ment that define the operating mode of the instrument.
These register settings and voltage levels control the
verti-
cal channel selection and deflection factors, the sweep
rate,
the triggering parameters, the readout activity, and
sequencing of the display. Loading the control data into
the various registers throughout the instrument is done
using a common serial data line (CD). Individual control
clock signals (CC) determine which register is loaded from
the common data line.
Coordination of the vertical, horizontal, and Z-Axis
(intensity) components of the display must be done in real
time.
Due to the speed of these display changes and the
precise timing relationships that must be maintained
between display events, direct sequencing of the display is
beyond the capabilities of the processor control. Instead,
control data from the processor is sent to the Display
Sequencer (a specialized integrated circuit) which responds
by setting up the various signals that control the stages
handling real-time display signals. The controlled stages
are stepped through a predefined sequence that is deter-
mined by the control data. Typically, as the sequence is
being executed, the Display Sequencer will be changing
vertical signal sources, Z-Axis intensity levels, triggering
sources, and horizontal sweep signal sources. The specific
activities being carried out by the Display Sequencer
depend on the display mode called for by the control data.
Vertical deflection for crt displays comes from one or
more of the four front-panel vertical inputs and, when
displaying readout information, from the Readout circuitry.
Signals applied to the front-panel Channel 1 and Channel
2 inputs are connected to their respective Preamplifiers via
processor-controlled Attenuator networks. Control data
from the Microprocessor defining the attenuation factor for
each channel is serially loaded into the Auxiliary Control
Register and then strobed into the Attenuator Mag-Latch
Relays in parallel. The relay switches of each Attenuator
network are either opened or closed, depending on the
data supplied to the Mag-Latch Relay Drivers. The relays
are magnetically latched and remain as set until new
con-
trol data is strobed in. The Auxiliary Control Register is
therefore available, and different mode data is clocked into
the register to set up other portions of the instrument.
Attenuated Channel 1 and Channel 2 input signals are
amplified by their respective Preamplifiers. The gain factor
for the Channel 1 and Channel 2 Preamplifiers is settable
by control data from the processor. The Channel 3 and
Channel 4 input signals are amplified by their respective
Preamplifiers by either of two gain factors set by control
bits from the Auxiliary Control Register. All four of these
preamplified signals are applied to the Vertical Channel
Switch where they are selected by the Display Sequencer
for display when required.
Each of the vertical signals is also applied to the A and
B Trigger circuitry via trigger pickoff outputs from the
Preamplifier stages. Any one of the signals may be
selected as the trigger SOURCE for either the A or the B
Trigger circuitry as directed by the Display Sequencer. The
line trigger signal provides an added trigger source for A
Sweeps only. Control data from the Microprocessor is
written to the Trigger circuitry to define the triggering
LEVEL, SLOPE, and COUPLING criteria. When the
selected trigger signal meets these requirements, a sweep
can be initiated. The Trigger circuit initiates both the A
Sweep and the B Sweep as required by the display mode
selected.
In the case of A Sweeps, the LO state of the THO
(trigger holdoff) signal from the Display Sequencer enables
the A Sweep circuit and the next A trigger initiates the
sweep. For B sweeps, and in the case of intensified
3a-4
To Next Page
Loading...
Need help?
General
