Tektronix 2467B

Theory of Operation—2465B/2467B Service
Reset Control
The Reset Control circuitry ensures that, at power up,
the Microprocessor begins program execution from a
known point in memory and with all the processor regis-
ters in known states. It also allows the processor to reset
itself when power is turned off so that the instrument
powers down in a known state.
POWER UP SEQUENCE. Reset generator U2240
generates the power-up reset. As power is applied to the
instrument U2240 tests the voltage at U2240 pin 7. The
reset generator forces U2240 pin 5 LO, and the LO is
applied to the processor RESET input (pin 40). After the
SENSE input reaches its nominal voltage level, the reset
condition continues to allow the microprocessor system
time to reset. The reset continues for the time determined
by C2350. The effect of power supply transients is
reduced by C2241. After the suplies reach their nominal
level and the delay period ends U2240 pin 5 goes HI. The
RESET signal to the processor then goes HI to enable
normal execution to begin, and the processor is directed to
the starting address of the power-up routine, which it then
performs.
POWER DOWN SEQUENCE. When the instrument
power switch is turned off, the PWR UP signal from J251
pin 12 immediately goes LO. This LO generates the NMI
(non-maskable interrupt) request to the processor on pin 6
which causes the processor to branch to the power-down
routine. Under direction of that routine, the processor
begins shutting down the instrument in an orderly fashion
before the power supply outputs can drop below the
operating thresholds. This routine disconnects the CH1
and CH2 50-fi input terminations to protect them from
accidental application of excessive voltage during storage
or bench handling.
As the operating voltages are falling, the Reset circuitry
must not generate a false RESET signal to the processor.
Such a restart when the power supply voltages are out-
side their normal operating range would produce
unpredictable processor operation that could alter the con-
tents of the battery backed up RAM. When the processor
has completed all the other power-down tasks, it finally
sets the PWR DOWN signal HI via U2310 (diagram 2).
This signal is applied to inverter U2540E at pin 11. Pin 10
of U2540E goes LO and immediately pulls pin 2 of Reset
Generator U2240 LO. Reset Generator U2240 immediately
switches state to assert the RESET signal to the proces-
sor. The RESET signal is held LO until the power supplies
have fully discharged.
For diagnostic purposes, the PWR DOWN reset signal
can be disabled. Moving jumper P503 to the DIAG (diag-
nostic) position keeps U2240 pin 2 HI. The RESET signal
is therefore held HI, and the processor can execute a
free-running NOP (no operation) loop without interruption if
the PWR DOWN bit is set HI while the Address Bus is
incrementing.
3a-6
Address Bus
Octal Latches, U2415 and U2425 are used to buffer the
address signals to the circuitry on the Processor Control
board as well as provide additional drive current for the
options. The RC network composed of R2465 and C2465
and inverter U2540B provide an additional >30 ns of
address hold time on the buffered address signals for the
options.
U2415 and U2425, along with Octal Latch U2405, allow
the buffered Address Bus and Microprocessor control sig-
nals to be disconnected from the microprocessor. This
allows in-circuit testing of the Processor Control board
without having to remove the Microprocessor.
Data Bus
Tri-state buffer U2350 is used to buffer the data signals
to the Microprocessor from other devices on the bus.
When not enabled, the device is switched to isolate the
processor from the buffered Data Bus. Buffer U2350 is
enabled via the Read-Write Latch U2440B when the pro-
cessor reads data from another device on the bus.
When the processor writes data onto the bus, Octal
Latch U2450 is enabled by the Read-Write Latch U2440B.
When the E (enable) signal at pin 11 of U2450 is HI, pro-
cessor data bits are passed asynchronously through the
latch to the buffered data bus. When the E signal goes LO,
data bits meeting setup times are latched into the device.
The latched Q outputs provide the required drive current
to the various devices on the bus and ensure that data
hold times are met for correct data transfer. When the
Read-Write Latch places a HI on pin 1 of U2450, latch
U2450 is disabled, and the outputs are switched to their
high-impedance state.
Data transfers to and from the processor may be inter-
rupted by removing Diag/Norm Jumper P503. This forces a
NOP (no operation) condition that is useful for verifying the
functionality of the processor (when a data-bus device is
suspected of causing a system failure) or for troubleshoot-
ing the Address Bus and Address Decode circuitry. Mov-
ing the jumper to the DIAG position disables both U2350
and U2450 and disconnects the microprocessor from the
buffered Data Bus. With the Data Bus disconnected, a
resistor network pulls the processor Data Bus lines (DO
through D7) to a NOP (no operation) instruction. A NOP
causes the Microprocessor to continuously increment
through its address field. The Address Decode circuitry
may then be checked to determine if it is operating prop-
erly.