Theory of
Operation—465B Service
Exclusive-NOR
Switching Circuit
The
Exclusive-NOR Switching
circuits produce a LO
pulse
on the ALT/CHOP select line
whenever a VERT
MODE
push button is either pressed
or
released
While the
ALT
Vertical
Mode is selected, the
LO
pulse
will enablethe
Chop oscillator, momentarily producing
clock pulses
which
enablethe
Vertical Switching Logic
circuit
to
select
the correct Vertical Mode
for the next display.
Assume
that the CH 1 VERT MODE
push button has
been pressed The
condition of Exclusive-NOR
circuit
U5235D is
as follows.
A
Hi is on pins
12 and 13 of U5235D,
and a HI is present
at output pin 1
1 ;
C51 35
has
charged to a
HI level through R51 35.
When the push
button is released,
a LO is immediately applied
to pin
12, but C5135 is
still
charged
to a HI level,
so
the
HI
remains
on pin 13. These
input conditions to the Excl usi ve-NOR
circuit will produce
a LO at
output pin 11 to enable
the Chop oscillator. Then
C5135 discharges toward
a LO level through R5135,
and
when the LO threshold
voltage is reached,
both inputs to
the Exclusive-NOR
circuit will
be
LO.
The output
of
U5235D will switch
back to HI, turning
off the Chop
oscillator.
When
the
X-Y Horizontal
Display
is selected,
—8
volts
is
applied through
R5212
to the XY select
input
of
the
Vertical Switching
Logic circuit
(placing it in the X-Y Mode
of operation) and
through the series
combination of R521
1
and
R5214 to the
ALT/CHOP select
to enable
the Chop
oscillator
if the Alternate
Vertical Mode
is selected
Scale-Factor
Switching
Circuit
The vertical
deflection factor
for each
channel is
indicated
by back-lighting
the
appropriate figures im-
printed
on the flange
of each VOLTS/DIV knob
Because
the operation
of the Channel
1 and
Channel
2 Scale-
Factor
Switching
circuits are
similar, only
the circuit
action
of the Channel
1 Scale-Factor
Switching
circuits is
described
When
CH 1 or ADD Vertical
Mode is selected,
or when
X-Y Horizontal
Display
Mode is selected,
8 volts is
applied
to the Q501
7 base
biasing
voltage divider network
composed of R51
14 and R5015 The
base of 0501 7 will
be
biased
negative,
saturating
Q5017. When
Q5017 is
saturated,
the XI
0 and XI scale-factor
LED DS9040
and
DS9060
will have
a return path
to ground through
the
transistor
and are enabled
(10X LED
or IX LED is lighted
depending on the
type of probe
or cable attached
to the
CH 1 OR X input
connector
)
The X-Y position of A TIME/DIV
switch
S6111 puts
-8
volts
on both Channel
1 and Channel
2 scale-factor
LED-enabling transistors
Q5017 and
Q5241 through
blocking
diodes
CR5115 and CR5116. This
allows the
appropriate scale-factor
LED to
be
illuminated
on both
CH
1 and CH
2
(10X
or IX)
With
either a coaxial cable
or IX probe
attached
to the
CH 1 OR X input connector,
the probe-coding
ring
portion
of the input
connector
is not contacted.
Q5057 will be
biased off
by the
8
volts through
R5055
A voltage
divider
network
composed of R5053,
R5041,
R5042. and
R5052
between
Q501 7 and the-
8 volt supply
will
biasQ5056into
conduction, the
IX LED
in
series
with
Q5056 will
be on.
The
10X
LED
is in parallel
with R5053, and
the voltage
drop
across R5053
will not
be sufficient
to cause the 10X
LED to
light
When a 10X probe
equipped with a
scale-factor-
switching connector
is attached to the CH
1 OR X input
connector, the probe
coding ring will
be contacted The
base of Q5057 will now
be connected to ground
through
R15102 and an
internal resistor located
within the probe
connector
body A
bias
voltage divider
is formed, biasing
Q5057 into saturation
The collector
of
Q5057 will
drop
to
about
-7.2
volts
This voltage level
is enough to light the
10X I ED. and when
It is applied
to
the
05056 base bias
voltage
divider composed
of R5042 and
R5052, it is
sufficient to bias
Q5056 off and
turn
off the
IX LED.
VERTICAL OUTPUT
AMPLIFIER
Introduction
The Vertical
Output Amplifier
circuit provides the
final
amplification
for the vertical deflection
signal. The circuit
includes the Delay
Line, part
of
the
Beam Finder circuitry,
and
part of
the
Trace Separation
circuitry.
Pushing the
BEAM FIND
button compresses
an overscanned display
to within
the viewing area
The Trace
Separation circuit
provides
vertical positioning
of the B
trace when the ALT
Horizontal
Display mode
is selected
Delay Line
Delay line
DL11405 (Diagram
3)
provides
approximate-
ly 120
nanoseconds delay
of the vertical
signal to allow the
Sweep
Generator circuits
sufficient
time to initiate
a
sweep
before the vertical
signal reaches
the deflection
plates
of the crt. When
using internal
triggering, the
instrument
is allowed to display
the leading
edge of the
signal originating
the trigger
pulse. Resistors
R2214
( R2206 below SN
B030000)
and R2218 (R2202
below SN
B030000) provide
forward termination
for the Delay
Line.
Input Amplifier
The
Input Amplifier
consists of integrated
circuit
amplifier
U2225
(U2210
below SN
B030000)
and the
frequency
compensation
network connected
across pins
2 and
3 Gain
Adjust
R2025
(R2005 below
SN
B030000)
sets
the
gain of
the amplifier
BEAM FIND
switch
S4075,
when
pressed,
reduces the
dynamic
swing capabilities
of
the stage,
thereby limiting
the
display
to
within
the display
area
on the crt
Trace
Separation
During
B sweep
the Trace
Separation
circuit
(Q2115,
02306, and
02308)
is
enabled
by the
alternate
pulse
on
3-10
REV A SEP 1979
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