Table 3-18. Board ID Memory Header Information (continued)
Header Field Name Size (bytes) Comments
DDR_INFO TYPE 1
Length 2 Offset to next header
DDR control 2 DDR Control Word
MAC_ADDR TYPE 1 Payload type
Length 2 Size of payload
MAC control 2 MAC header control word
MAC_adrs 192 MAC address of AM64x/AM243x PRG2
END_LIST TYPE 1 End Marker
3.4.9 Ethernet Interface
Three Ethernet PHYs terminated to RJ45 connectors with integrated magnetics is supported on the EVM.
Figure 3-18. Ethernet Interface - CPSW Domain
The first PHY (connected to RJ45 connector J14) is interfaced to the CPSW_RGMII1 port of the SoC. The
DP83867 PHY has been selected for this interface based on its ability to configure the Tx and Rx Delays. Since
the CPSW_RGMII1_RX port is also multiplexed with PRG0 signals, a mux is needed to select the path from the
SoC to this PHY (in CPSW mode) or to the HSE connector (PRG0 mode). The selection is done using a GPIO
from the 24 bit IO expander.
The second PHY (connected to stacked RJ45 connector J21B) is interfaced to the PRG1_RGMII2 port of the
SoC. This port is directly multiplexed with the CPSW_RGMII2 port. In order to select between CPSW and PRG
operation, we need to multiplex the MDIO MDC signals from each controller to this PHY and the mux shall be
controlled by a GPIO from IO expander. PRG1_RGMII2 is also internally multiplexed with PRG1_MII signals.
The objective of the PHY used to connect this port is that the PHY should support both RGMII and MII modes,
hence DP83869 (48 pin) PHY is selected.
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System Description
SPRUIX0C – FEBRUARY 2021 – REVISED JUNE 2021
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AM64x/AM243x GP EVM User's Guide 33
Copyright © 2021 Texas Instruments Incorporated
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