Advisory Memory: Prefetching Beyond Valid Memory
Revisions Affected
0, A, B, C
Details The C28x CPU prefetches instructions beyond those currently active in its pipeline. If
the prefetch occurs past the end of valid memory, then the CPU may receive an invalid
opcode.
Workarounds M1, GS11, GS15 – The prefetch queue is 8 x16 words in depth. Therefore, code should
not come within 8 words of the end of valid memory. Prefetching across the boundary
between two valid memory blocks is all right.
Example 1: M1 ends at address 0x7FF and is not followed by another memory block.
Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8–0x7FF
should not be used for code.
Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0 can
be stored up to and including address 0x3FF. Code can also cross into M1, up to and
including address 0x7F7.
Flash – The prefetch queue is 16 x16 words in depth. Therefore, code should not
come within 16 words of the end of valid memory; otherwise, it generates a Flash ECC
uncorrectable error.
Table 3-2. Memories Impacted by Advisory
MEMORY TYPE ADDRESSES IMPACTED
F28378D
F28377D
F28375D
F28376D
F28374D
M1 0x0000 07F8–0x0000 07FF Yes Yes
GS11 0x0001 7FF8–0x0001 7FFF No Yes
GS15 0x0001 BFF8–0x0001 BFFF Yes N/A
Flash 0x000B FFF0–0x000B FFFF Yes N/A
Silicon Revision C Usage Notes and Advisories www.ti.com
28 TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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