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Analog Front End IC TMS37122 - Reference Guide August ’01
2.5 Wake Detector
Wake Detector 1…3, which are enabled by the Configuration Memory, are activated by the
Control Unit when WDEEN is activated. The first stage of the Wake Detector is an Automatic
Gain Control (AGC) Amplifier, which is initially at maximum amplification (see Figure 11).
In case a RF oscillation appears at the input (RF) the Automatic Gain Control starts to regu-
late. After a run-in time (tPdly) the regulation is stable and the EOB Detector is enabled. If
the amplitude of the RF Signal now exceeds a predetermined level (VWAKEA) a Clock Re-
generator is enabled.
At Wake Detector 1 the level can be configured by the Configuration Memory (Level Adjust/
Detect). Wake Detector 2 and 3 have maximum sensitivity.
The clocks provided by the Clock Regenerator are counted and supervised by the Clock Su-
pervision circuit, which activates at a certain state the EOB Detector. An analog watchdog
detects missing clocks. If at least 2 to 4 clocks are missed, the counter resets and restarts
counting. If the clock counter succeeds in counting to cWdly the WAKEI signal is set. Once
set, only WDEENIx can reset the WAKEIx signal.
Figure 11: Block schematic of Wake Detector
AGC
AMPLIFIER
CLOCK
REGENERATOR
CLOCK
SUPERVISION
EOB
DETECTOR
LEVEL
DETECTOR
VWAKEB
VWAKEA
EN
WAKE DETECTOR
LEVEL
ADJUST/ DETECT
CHECK
WAKEBx
WAKEBx
CLKIx
WAKEIx
EOBIx
CONTROL UNIT
3DDBD01A.DRW
RFx
1pF
WDEENIx
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