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Analog Front End IC TMS37122 - Reference Guide August ’01
4.2.3.4 IC
Parameter Sign Note Min Nom Max Unit
Battery Voltage VBAT versus DG 2.0 3.0 4.0 V
Battery Voltage Test VBAT Tst 2.5 4.0
Power Supply Ripple Vripple 50 mVpp
High level input voltage VIH
WDEEN, MOD,
TX,VBAT=
2.0 ... 4V
0.95 x
VBAT
1.05 x
VBAT
V
Low level input voltage VIL
WDEEN, MOD,
TX, VBAT =
2.0 … 4V
0
0.05 x
VBAT
V
Output Load Capacitance COL
all outputs except
VCCO
10 pF
Output Load Resistance RL
all outputs except
VCCO
100 kΩ
Output Current IVCCO VCCO 1 mA
Supply Voltage for Trim/
Test
VCL
with respect to DG,
25 ºC 2.5
VCL=
VBAT
=4
6V
High level input voltage,
TDAT, TCLK, TEN
VIH
VBAT=
2…4V
0.95 x
VBAT
1.05 x
VBAT
V
Low level input voltage,
TDAT, TCLK, TEN
VIL
VBAT=
2…4V
0
0.05 x
VBAT
V
Clock frequency fTC TCLK 100 134.2 1000 kHz
Rise and fall time, TDAT,
TCLK, TEN
tf 500 ns
Programming Voltage Vpp TEN pin 15 16 17 V
VPP Rise Time trVPP VBAT to VPP 1 5 ms
VPP Fall Time tfVPP VPP to VBAT 1 ms
Programming Time tPRG 15 20 ms
Pluck Time tpluck
PTx18,
PTx28,
PTx38
100 1000 ns
Reset Time treset WDEEN=0 10
µs
Max. EOBA duration during
Wake Pattern Detection
toffTRP 0.5 ms
Max. EOBA duration in
Transparent Mode
toffTRP WAKE=high 1 ms