Silicon Image
Confidential for Philips
Consumer Electronics
Internal Use Only
SiI9185A 3:1 HDMI 1.3 Switch
Preliminary Data Sheet
Silicon Image, Inc.
Normal and Standby Modes
There are two power modes: P0 for Normal mode and P1 for Standby mode. The Normal mode, P0, is enabled when one
of three RX ports is selected to provide audio/visual stream and HDCP/DDC information to the TX port as shown in
Table 2. In Normal mode, all power supplies (AVCC33, AVCC18, and DVCC18) must be applied. In P0, all of the
functional blocks are active: PLL, data-paths, local I
2
C and DDC relaying, and CEC.
Setting PSEL[1:0] = 11 sets the SiI9185A into low-power standby mode (P1). In P1, all of the receive ports transition to
the low-power state and the Tx outputs are disabled (Hi-Z). The purpose of P1 is to make the SiI9185A alive to power
the DDC and CEC interfaces only, while the data-path of the SiI9185A (analog and digital) consumes minimum power.
The I
2
C and DDC relay require logic power (DVCC18), I/O power (AVCC33), and OSC power (AVCC18). Because
none of the receive ports are selected in P1, the PLL does not get an input clock, and shuts itself down. In Standalone
mode P1, the HPD outputs are deasserted (set to 0).
I2CADDR/TPWR Control Pin
The I2CADDR/TPWR pin is sampled on the rising edge of RESET# to determine bit two of the default base address for
the I
2
C interface. If I2CADDR/TPWR is low on the rising edge of RESET#, the I
2
C interface address for the PHY and
Chip Control registers is set to 0xD0, the I
2
C interface address for the EDID Controller is set to 0xE0, and the I
2
C
interface address for the CEC Registers is set to 0xC0. If I2CADDR/TPWR is high on the rising edge of RESET#, the
I
2
C interface addresses are set to 0xD4, 0xE4, and 0xC4, respectively. The actual address values in both modes are
shown in Table 1 on page 8.
Once RESET# goes high, the I2CADDR/TPWR pin becomes the normal output Transmit Power (TPWR). TPWR is an
output from the SiI9185A that tells the transmit side that the selected receive port is actually connected. The switching
time between RPWR0/1/2 and TPWR is determined by the PLL lock behavior and logic that detects the presence of a
valid input signal (see RPWR[0:2](+5V) and TPWR(+5V) control pins on page 11 for a description).
CEC Transceiver Control Pins
The CEC (Consumer Electronics Control) interface is composed of the bidirectional signals CEC_D, CEC_A, and a
local I
2
C interface. CEC_D is the CEC signal from a CEC Master (microcontroller), and CEC_A is an electrical spec-
compliant CEC signal connected to all CEC Slave devices. The CEC_A signal drives the CEC pins from all three
HDMI/DVI Rx connectors at the same time.
The CEC interface has two modes: CEC_D relay mode and CEC API mode. In CEC_D relay mode, the SiI9185A is
simply a CEC transceiver, and all software must be implemented on the host CPU. In CEC API mode, the SiI9185A
performs all the low-level CEC control, and the host CPU must read and write to high-level I
2
C registers to send and
receive CEC commands. In CEC_D relay mode, the CEC interface only monitors the CEC signal direction and provides
appropriate timing between events. In CEC API mode, the local I
2
C provides CEC commands to the CEC interface block
to generate CEC signaling to the CEC_A port, and the local I
2
C monitors the CEC value in the register map.
HPD Control Pin
The Hot Plug Detection (HPD) signal is provided in the HDMI/DVI connector to provide a signal to the host that the
EDID is readable. In the SiI9185A there are three outputs for the receive side (HPD0, HPD1, and HPD2), and one input
from the transmit side (HPDIN). HPDIN from the Tx port can be relayed to the selected Rx port, or the HPD[0:2]
outputs can be set using registers. In Standalone mode, the HPD outputs of non-selected Rx ports are set to low, so no
EDID transaction or HDCP authentication is initiated for non-selected ports until that port is selected. The default signal
level of the HPD output is low and the high signal level is 3.3V CMOS (and is +5V tolerant).
In internal SiI9185A applications, the HPDIN pin may not to be brought out as an external pin. In this case, the local I
2
C
directly controls the HPD output of selected and/or non-selected ports. But in external HDMI switch applications, the
HDMI receiver on the video processing board provides an HPD signal input to the HDMI switch board, and the HPD
input is re-directed to one of the selected receive ports.
In I
2
C Control mode, the state of the HPD pins is controlled by setting the HP_CTRL_x bits in the Hot Plug Detect
Output Control register, where x is the channel number. Each of the HPD0, HPD1, and HPD2 signals is independently
controllable. For example, all three signals could be high at the same time.
HPD output pins have 1-kΩ series resistors integrated to comply with the impedance requirement specified in version 1.3
of the HDMI Specification.
Table 3 on page 11 shows the possible states of the HPD control signals.
10 © 2007 Silicon Image, Inc. CONFIDENTIAL SiI-DS-1016-0.80
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