TYAN S7010 - Page 57

57
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SDR Monitoring Next Page
Main Advanced PCI/PnP Boot Security Chipset Exit
ID# NAME READING STATUS
02
01
03
04
0C
0B
0D
0E
0F
10
20
21
22
23
24
25
26
CPU1 below Tmax
CPU0 below Tmax
PCI Area 1 (RT2)
PCI Area 2 (RT4)
CPU1 VCORE
CPU0 VCORE
3.3V
+12V
VBAT
5V
Sys. 1 (CPU0)
Sys. 2 (CPU1)
Sys. 3 (Front 1)
Sys. 4 (Front 2)
Sys. 5 (Rear 1)
Sys. 6
Sys. 7
: xx
o
C
: xx
o
C
: xx
o
C
: xx
o
C
: x.xxx V
: x.xxx V
: x.xxx V
: x.xxx V
: x.xxx V
: x.xxx V
: xxxx RPM
: xxxx RPM
: xxxx RPM
: xxxx RPM
: xxxx RPM
: xxxx RPM
: xxxx RPM
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
SDR Monitoring Next Page
← → Select Screen
↑↓ Select Item
+/- Change Option
Tab Select Field
F1 General Help
F10 Save and Exit
ESC Exit
Main Advanced PCI/PnP Boot Security Chipset Exit
ID# NAME READING STATUS
27
28
29
Sys. 8
Sys. 9
Sys. 10
: xxxx RPM
: xxxx RPM
: xxxx RPM
xx
xx
xx
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