ZED-F9K-Integration manual
Baud rate Data bits Parity Stop bits
230400 8 none 1
460800 8 none 1
921600 8 none 1
Table 15: Possible UART interface configurations
The default baud rate is 38400 baud. To prevent buffering problems it is recommended not
to run at a lower baud rate than the default.
Note that for protocols such as NMEA or UBX, it does not make sense to change the default word
length values (data bits) since these properties are defined by the protocol and not by the electrical
interface.
If the amount of data configured is too much for a certain port's bandwidth (e.g. all UBX messages
output on a UART port with a baud rate of 9600), the buffer will fill up. Once the buffer space is
exceeded, new messages to be sent will be dropped. To prevent message loss, the baud rate and
communication speed or the number of enabled messages should be carefully selected so that the
expected number of bytes can be transmitted in less than one second.
3.4.2 I2C interface
An I2C interface is available for communication with an external host CPU or u-blox cellular modules.
The interface can be operated in slave mode only. The I2C protocol and electrical interface are fully
compatible with the I2C industry standard fast mode. Since the maximum SCL clock frequency
is 400 kHz, the maximum transfer rate is 400 kb/s. The SCL and SDA pins have internal pull-up
resistors which should be sufficient for most applications. However, depending on the speed of the
host and the load on the I2C lines additional external pull-up resistors may be necessary.
To use the I2C interface D_SEL pin must be left open.
In designs where the host uses the same I2C bus to communicate with more than one u-
blox receiver, the I2C slave address for each receiver must be configured to a different value.
Typically most u-blox receivers are configured to the same default I2C slave address value. To
poll or set the I2C slave address, use the CFG-I2C-ADDRESS configuration item (see ZED-F9K
Interface description [2]).
The CFG-I2C-ADDRESS configuration item is an 8-bit value containing the I2C slave address
in 7 most significant bits, and the read/write flag in the least significant bit.
3.4.2.1 I2C register layout
The I2C interface allows 256 registers to be addressed. As shown in Figure 12, only three of these
are currently implemented.
The data registers 0 to 252 at addresses 0x00 to 0xFC contain reserved information, the result from
their reading is currently undefined. The data registers 0 to 252 are 1 byte wide.
At addresses 0xFD and 0xFE it is possible to read the currently available number of bytes.
The register at address 0xFF allows the data stream to be read. If there is no data awaiting
transmission from the receiver, then this register delivers value 0xFF, which cannot be the first byte
of a valid message. If the message data is ready for transmission, the successive reads of register
0xFF will deliver the waiting message data.
Do not use registers 0x00 to 0xFC. They are reserved for future use and they do not
currently provide any meaningful data.
UBX-20046189 - R01
3 Receiver functionality Page 36 of 105
C1-Public Early production information
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