THEORY OF OPERATION
4-16
Versapulse Select Service Manual
0621-499-01 01/94
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FIRING A LAMP - Firing consists of selecting the appropriate lamp for discharge, then providing a trigger to
cause the discharge at the appropriate time to provide the selected pulse interval.
Each flash lamp has a triggering SCR in series with it. The four sets of flash lamps and SCR's are connected in
parallel (as shown in the block diagram). Each SCR gate is connected to a trigger circuit (located on the
Trigger PCB). When triggered, the trigger circuit gates its associated SCR on, establishing a current path for
discharge of the main charging cap through the associated lamp.
Prior to firing, the main processor determines which head is to be fired next and connects the /FIREPLS/
signal to the appropriate trigger circuit. The selection is made by the U43 digital I/O outputs LASLCTA,
LASLCTB, LASLTC. These three lines provide a binary coded input to decoder/multiplexer U42. U42
decodes the select inputs to determine which of its four connected outputs (Y1, Y2, Y3, Y4) to connect with
the /FIREPLS/ input. The four output lines are the trigger inputs to the four trigger circuits. The main
processor uses U42 to route the /FIREPLS/ signal to the appropriate trigger circuit.
Each trigger line out of U42 is attached to an infrared transmitter (XTRM1 through 4). Optical fibers carry the
signal from the XTRM's to infrared receivers (RECV 1 through 4) on the Isolated Trigger PCB.
The pulse interval is the period of time that falls between the pulses during firing. For example, a 20 Hz
pulse rate has a pulse interval 50 milliseconds, i.e., the /FIREPLS/ signal should occur every 50 milliseconds.
The /FIREPLS/ interval is monitored by both the main and safety processors.
The main processor asserts /FIREPLS/ low out of Digital I/O chip U43 (pin 33) to fire the selected head.
Assume head 1 is to be fired. The /FIREPLS/ signal is routed through the decoder (U42) out on pin 14 to pin
1 of amplifier U50 and then on to XTRM1 (turns on). At the Isolated Trigger PCB, the infrared signal turns on
RECV1, to turn on gate Q1. Q1 on connects the SCR1 gate to 30 VDC through R2. This triggers the SCR,
providing a discharge path for the main charging capacitor through Flash Lamp 1.
MONITORED SIGNALS - The HVPS provides several digital status signals back to the control circuit as well
as an analog capacitor charge feedback signal.
TEMP OL - The HVPS grounds this line to indicate an overtemperature condition has been detected
at the HVPS. It enters the CPU PCB at J2-6 and goes through opto-isolator U8 to become /HVPTOL/
(low when the fault condition exists), input to digital I/O U44 pin 22.
CURRENT OL - The HVPS grounds this line when the HVPS is operated at too high a duty cycle. It
enters the Controller at J2-10 and goes through opto-isolator U8 to become /HVPCOL/ (low when
the fault condition exists), input to digital I/O U44 pin 23.
NO CAP - The HVPS grounds this line when the HVPS detects a problem on the output line to the
charging capacitor. It enters the CPU PCB at J2-12 and goes through opto-isolator U11 /HVPNCR/
(low when the fault condition exists), input to digital I/O U44 pin 24.
CHARGE - The HVPS grounds this line when the main charging capacitor has been charged to the
requested level. It enters the CPU PCB at J2-9 and goes through opto-isolator U99 to become /
HVPCRI/, input to digital I/O U44 pin 21.
12/95
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