Wang 5536 - Page 27

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Row Address Select (RAS) and Column Address Select (CAS) logic is
employed to address main memory. RAS and CAS lines enable 16-bit
addresses to be processed in 8-bit, half-address form, permitting 16-bit
main memory addresses to be written and read with the 8-bit Z80A CPU.
RAS/CAS logic transfers high-order and low-order address bits through
the same chip pins at different times.
RAS/CAS cycles are required whenever main memory is addressed. Main
memory is addressed during these operations:
o CPU instruction fetch/refresh cycle
o CPU data read
o CPU data write
o DMA trans fer.
A CPU instruction fetch is requested for as long as th~ CPU indicates
that an instruction address is on the address bus. This request is
delayed by one CPU clock time.
CRT Memory
CRT Memory is discussed in Section 2.3.1.5. If selected, CRT RAM
occupies addresses 48K to 64K of the Z80A's address range. This portion
of memory can be addressed only by the CPU and by CRT scan logic. No
DMA path can access CRT memory. The CPU writes characters that are to
appear on the screen, and may read characters that are already being
displayed.
Although CRT memory contains fewer than 4K display characters it
requires 16K of address space. The additional addressing is needed for
attribute memory and to support the row/column addressing method. CRT
memory-address space is mapped into the top 16K of main memory to
simplify CRT display update by the CPU. Special logic permits the top
16K of memory to be switched from CRT memory to additional main
(program) memory when the workstation is used for data processing
applications.
o PROM Diagnostic Memory (Used In-House Only)
PROM or Diagnostic Memory, when present, permits a power-up diagnostic
and a local mode of operation to be employed with the workstation.
The three memory categories overlap. When power is applied the (64K)
workstation has 48K of main memory and 16K of CRT memory.
The PROM overlays the bottom 2K of main memory.
selected, the bottom 2K of RAM cannot be read,
written. The PROM can be selected at any time.
If the PROM has been
although it can be
Both main and CRT memories have a parity bit. This bit is checked for
data integrity on every read. PROM memory is not checked for parity •
When a parity error is detected, the CPU stops and all characters are
underlined on the CRT display. When the PROM is read, memory parity
errors are cleared.
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