Xilinx Kintex-7 FPGA KC705

36 www.xilinx.com KC705 Getting Started Guide
UG883 (v4.0.1) May 28, 2014
Advanced Bring-up Using the Base Targeted Reference Design
4. Click the PCIe Statistics tab to view data transfer numbers with varying packet
sizes on the PCIe interface (Figure 26).
The system performance of the Kintex-7 FPGA Base TRD has now been evaluated using
the pre-built demonstration design bit file.
Now that the Kintex-7 FPGA Base TRD demonstration has been set up and evaluated, the
design can be modified. Before the design can be modified, make sure to install the Vivado
Design Suite on a PC. It is not required that tools be installed on the PC system in which the
KC705 evaluation board is plugged in by way of the PCIe edge connector.
X-Ref Target - Figure 26
Figure 26: PCIe Statistics in the Performance Monitor
UG883_26_121112
Send Feedback