Xilinx SP605 User Guide

SP605 Hardware User Guide www.xilinx.com 61
UG526 (v1.1.1) February 1, 2010
Appendix C
SP605 Master UCF
The UCF template is provided for designs that target the SP605. Net names provided in the
constraints below correlate with net names on the SP605 rev. C schematic. On identifying
the appropriate pins, the net names below should be replaced with net names in the user
RTL. See the Constraints Guide
for more information.
NET "CLK_33MHZ_SYSACE" LOC = "N19"; ## 93 on U17
NET "CPU_RESET" LOC = "H8"; ## 2 on SW6 pushbutton (active-high)
##
NET "DVI_D0" LOC = "K16"; ## 63 on U31 (thru series R39 47.5 ohm)
NET "DVI_D1" LOC = "U19"; ## 62 on U31 (thru series R38 47.5 ohm)
NET "DVI_D2" LOC = "T20"; ## 61 on U31 (thru series R37 47.5 ohm)
NET "DVI_D3" LOC = "N16"; ## 60 on U31 (thru series R36 47.5 ohm)
NET "DVI_D4" LOC = "P16"; ## 59 on U31 (thru series R35 47.5 ohm)
NET "DVI_D5" LOC = "M17"; ## 58 on U31 (thru series R34 47.5 ohm)
NET "DVI_D6" LOC = "M18"; ## 55 on U31 (thru series R33 47.5 ohm)
NET "DVI_D7" LOC = "R15"; ## 54 on U31 (thru series R32 47.5 ohm)
NET "DVI_D8" LOC = "R16"; ## 53 on U31 (thru series R31 47.5 ohm)
NET "DVI_D9" LOC = "P17"; ## 52 on U31 (thru series R30 47.5 ohm)
NET "DVI_D10" LOC = "P18"; ## 51 on U31 (thru series R29 47.5 ohm)
NET "DVI_D11" LOC = "R17"; ## 50 on U31 (thru series R28 47.5 ohm)
NET "DVI_DE" LOC = "J17"; ## 2 on U31 (thru series R40 47.5 ohm)
NET "DVI_GPIO1" LOC = "D22"; ## 18 on U31
NET "DVI_H" LOC = "J16"; ## 4 on U31 (thru series R41 47.5 ohm)
NET "DVI_RESET_B" LOC = "L15"; ## 13 on U31
NET "DVI_V" LOC = "B22"; ## 5 on U31 (thru series R42 47.5 ohm)
NET "DVI_XCLK_N" LOC = "C22"; ## 56 on U31
NET "DVI_XCLK_P" LOC = "C20"; ## 57 on U31
##
NET "FLASH_A0" LOC = "N22"; ## 29 on U25
NET "FLASH_A1" LOC = "N20"; ## 25 on U25
NET "FLASH_A2" LOC = "M22"; ## 24 on U25
NET "FLASH_A3" LOC = "M21"; ## 23 on U25
NET "FLASH_A4" LOC = "L19"; ## 22 on U25
NET "FLASH_A5" LOC = "K20"; ## 21 on U25
NET "FLASH_A6" LOC = "H22"; ## 20 on U25
NET "FLASH_A7" LOC = "H21"; ## 19 on U25
NET "FLASH_A8" LOC = "L17"; ## 8 on U25
NET "FLASH_A9" LOC = "K17"; ## 7 on U25
NET "FLASH_A10" LOC = "G22"; ## 6 on U25
NET "FLASH_A11" LOC = "G20"; ## 5 on U25
NET "FLASH_A12" LOC = "K18"; ## 4 on U25
NET "FLASH_A13" LOC = "K19"; ## 3 on U25
NET "FLASH_A14" LOC = "H20"; ## 2 on U25
NET "FLASH_A15" LOC = "J19"; ## 1 on U25
NET "FLASH_A16" LOC = "E22"; ## 55 on U25
NET "FLASH_A17" LOC = "E20"; ## 18 on U25
NET "FLASH_A18" LOC = "F22"; ## 17 on U25
NET "FLASH_A19" LOC = "F21"; ## 16 on U25
NET "FLASH_A20" LOC = "H19"; ## 11 on U25
NET "FLASH_A21" LOC = "H18"; ## 10 on U25
NET "FLASH_A22" LOC = "F20"; ## 9 on U25
NET "FLASH_A23" LOC = "G19"; ## 26 on U25
NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## 34 on U25, 8 on U32 (thru series R132 100 ohm), 6 on J17
NET "FPGA_D1_MISO2" LOC = "R13"; ## 36 on U25, 3 on J17
NET "FPGA_D2_MISO3" LOC = "T14"; ## 39 on U25, 2 on J17
NET "FLASH_D3" LOC = "AA6"; ## 41 on U25
NET "FLASH_D4" LOC = "AB6"; ## 47 on U25
NET "FLASH_D5" LOC = "Y5"; ## 49 on U25
NET "FLASH_D6" LOC = "AB5"; ## 51 on U25
NET "FLASH_D7" LOC = "W9"; ## 53 on U25
NET "FLASH_D8" LOC = "T7"; ## 35 on U25
NET "FLASH_D9" LOC = "U6"; ## 37 on U25
NET "FLASH_D10" LOC = "AB19"; ## 40 on U25
NET "FLASH_D11" LOC = "AA18"; ## 42 on U25
NET "FLASH_D12" LOC = "AB18"; ## 48 on U25
NET "FLASH_D13" LOC = "Y13"; ## 50 on U25
NET "FLASH_D14" LOC = "AA12"; ## 52 on U25
NET "FLASH_D15" LOC = "AB12"; ## 54 on U25
NET "FLASH_WAIT" LOC = "T18"; ## 56 on U25

Xilinx SP605 Specifications

General

Brand	Xilinx
Model	SP605
Category	Motherboard
Language	English