Xilinx SP605 - Appendix C: Xilinx Design Constraints; Overview

SP605 Hardware User Guide www.xilinx.com 65
UG526 (v1.1.1) February 1, 2010
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NET "SYSCLK_N" LOC = "K22"; ##
NET "SYSCLK_P" LOC = "K21"; ##
##
NET "USB_1_CTS" LOC = "F18"; ##
NET "USB_1_RTS" LOC = "F19"; ##
NET "USB_1_RX" LOC = "B21"; ##
NET "USB_1_TX" LOC = "H17"; ##
##
NET "USER_CLOCK" LOC = "AB13"; ##
NET "USER_SMA_CLOCK_N" LOC = "M19"; ##
NET "USER_SMA_CLOCK_P" LOC = "M20"; ##
NET "USER_SMA_GPIO_N" LOC = "A3"; ##
NET "USER_SMA_GPIO_P" LOC = "B3"; ##
Note:
1. Pullup and pulldown resistors which branch from nets are not included
2. Pullup and pulldown resistors to a single point power or GND are included
3. Series resistors are included
4. DNP = do not populate, no component will be installed on the PCB at this location