Xilinx VC707 User Manual

108 www.xilinx.com VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
Appendix C: Master Constraints File Listing
set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
set_property PACKAGE_PIN B17 [get_ports DDR3_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
set_property PACKAGE_PIN A15 [get_ports DDR3_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
set_property PACKAGE_PIN A21 [get_ports DDR3_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
set_property PACKAGE_PIN F17 [get_ports DDR3_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
set_property PACKAGE_PIN E17 [get_ports DDR3_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
set_property PACKAGE_PIN D21 [get_ports DDR3_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
set_property PACKAGE_PIN C21 [get_ports DDR3_BA1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
set_property PACKAGE_PIN D18 [get_ports DDR3_BA2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
set_property PACKAGE_PIN J17 [get_ports DDR3_S0_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
set_property PACKAGE_PIN J20 [get_ports DDR3_S1_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
#USB
set_property PACKAGE_PIN BA35 [get_ports USB_SMSC_NXT]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_NXT]
set_property PACKAGE_PIN BB36 [get_ports USB_SMSC_RESET_B]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_RESET_B]
set_property PACKAGE_PIN BB32 [get_ports USB_SMSC_STP]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_STP]
set_property PACKAGE_PIN BB33 [get_ports USB_SMSC_DIR]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DIR]
set_property PACKAGE_PIN AV34 [get_ports USB_SMSC_REFCLK_OPTION]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_REFCLK_OPTION]
set_property PACKAGE_PIN AY32 [get_ports USB_SMSC_CLKOUT]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_CLKOUT]
set_property PACKAGE_PIN AV36 [get_ports USB_SMSC_DATA0]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA0]
set_property PACKAGE_PIN AW36 [get_ports USB_SMSC_DATA1]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA1]
set_property PACKAGE_PIN BA34 [get_ports USB_SMSC_DATA2]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA2]
set_property PACKAGE_PIN BB34 [get_ports USB_SMSC_DATA3]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA3]
set_property PACKAGE_PIN BA36 [get_ports USB_SMSC_DATA4]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA4]
set_property PACKAGE_PIN AT34 [get_ports USB_SMSC_DATA5]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA5]
set_property PACKAGE_PIN AY35 [get_ports USB_SMSC_DATA6]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA6]
set_property PACKAGE_PIN AW35 [get_ports USB_SMSC_DATA7]
set_property IOSTANDARD LVCMOS18 [get_ports USB_SMSC_DATA7]
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Xilinx VC707 Specifications

General

Brand	Xilinx
Model	VC707
Category	Motherboard
Language	English