Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 68
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
Ethernet 10G Output Pipeline
The Ethernet 10G output pipeline is shown in Figure 5-11.
This pipeline consists of two main components—the 10G/25G high speed Ethernet
Subsystem and AXI DMA, each shared with the Ethernet 10G input/capture pipeline. Refer
to Ethernet 10G Input/Capture Pipeline for more information and for the configuration of
each component.
X-Ref Target - Figure 5-11
Figure 5-11: Ethernet 10G Output Pipeline
Ethernet 10G/25G
Subsystem
AXI
DMA
HPM0/1
HP0
PL
AXI-Lite AXI-Stream AXI-MM
128
128
32
6464
Ethernet 10G Output/Capture Pipeline
PS
X21947-120318X21947-042419
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C