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SM 700820-01E
(2) AFC Board Assembly
The AFC Board Assembly consists of the AFC (Analog Front-end Controller), the D/A
converter, the Trigger compactor, the TV Trigger circuits, and so on.
The AFC generates the control signals for the ATT Board Assembly and the Trigger
circuit. The PWM output of the D/A converter is also supplied by the AFC. The D/A
converter supplies, by using the PWM method, the offset voltage, the Gain control
voltage, and the threshold voltage of the Trigger comparator. One Trigger comparator is
mounted for each channel. Only for CH1, one more comparator is boarded for the
Window Trigger.
The TV Trigger circuit is also incorporated for CH1. The TV trigger corresponds to the
PAL, NTSC, and HDTV broadcasting methods.
4.3 Digital Section
(1) Trigger Board Assembly
The Trigger logic circuit, the Timebase circuit and the Timing control circuit are
incorporated in the Trigger Board Assembly. In addtion, it incorporates the reference
voltage generator and the D/A converter for generating the threshold voltage of the logic
probes.
The timebase clock is generated by the 200 MHz crystal oscillator. The 200 MHz
clock or the 250 MHz which is the fifth over-tone of 50 MHz divided the original clock,
200 MHz, is supplied for the clock of the A/D converter. In the 500MSps Interleave
mode, the 250 MHz is used and the 200 MHz is utilized in the other modes. Addition-
ally, the external clock sampling is also possible.
In the trigger logic part, trigger is detected in the condition of the simple trigger menu or
the enhanced trigger menu. The time measuring between the sampling clock and the
trigger edge is also implemented.
(2) ACQ Board Assembly
The ACQ Board Assembly includes the analog multiplexer circuit, the A/D converter,
the ECL rate-reducer, the ADP (Acquisition Data Processor), the ACL (Acquisition
Control Logic), the Work memory, and so on. One ACQ Board Assembly consists of
the two channels components which executes the interleave function.
The output signal from A/D converter is decreased to the half speed at the ECL rate-
reducer and the signal comes into the ADP. The ADP implements the data thinning, the
Envelop processing, or the Box average processing, in accordance with the sampling
rate. The output data from the ADP are written to the acquisition memories.
The ACL generates the control signal of the acquisition memories and writes the data
into the memories. It sorts the data in the acquisition memories after the acquisition.
(History Memory function) Furthermore, the ACL executes the P-P compression
processing and the histogram processing for the measurement function. The result data
are written to the work memories.
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