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SM 700820-01E
PRINCIPLE OF THE OPERATION
(4) Synthesized Timing Generator (STG)
It is the ECL gate array which aims to implement the clock signal supply, the trigger
synchronizing, the time measuring.
(5) Time to Voltage Converter (TVC)
It is the Analog IC which aim to execute the T-V converting for time measuring between
the sampling clock and trigger signal.
(6) First Trigger Logic (FTL)
It is the ECL gate array which performs “OR” trigger, “Parallel Pattern” trigger, and
“Pulse Width” trigger.
(7) Acquisition Data Processor (ADP)
It is the CMOS gate array which aims to process the data from the A/D converters so
that the data can be written to the acquisition memories. One ADP is in charge of
*
a pair
of channels for the interleave function. Normally, the ADP produces the data at the one
eighth speed rate of the A/D converting. It also performs thinning, Envelop function,
and Box-Average processing.
(8) Acquisition Control Logic (ACL)
It is the CMOS gate array which aims to perform the Acquisition memories control, the
P-P compression processing, and Histogram processing. The P-P compression data and
the Histogram data for the parameter measurement are written to the Work memories.
*) The following channel combinations are pairs for the Interleave function.
70082_: CH1 and CH2
70084_: CH1 and CH3, CH2 and CH4
70086_: CH1 and CH4, CH2 and CH5, CH3 and CH6
70088_: CH1 and CH5, CH2 and CH6, CH3 and CH7, CH4 and CH8
4.4 Functions of Each Gate Array
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