Page
3.5
General Theory of Operation
CPU
Memory Access
The
CPU
cannot interfere with the transfer of data from the
RAM
to the
registers (CRTC control), but must write
all
of the data into the
RAM.
The
CPU
is
allowed access to the
RAM
for 245 nanoseconds of each
512
nanosecond access period. During this time, the
CPU
can write one
byte
of data into one of the RAMs. This means that to fill the screen,
the
CPU
must write into the
RAM
4000 times (80 character bytes
and
80
attribute bytes by
25
lines).
To
clear the screen, the
CPU
must write zeros to
all
attribute
RAM
loca-
tions. To scroll the screen, all data must
be
moved up one line position
so
that new data can
be
written to the last line.
CRTC Registers
The
CRTC manages the memory and controls the display. The action
of the CRTC
is
controlled by its 18 internal registers. All CRTC internal
registers are set by the CPU at power
up.
The
internal registers are:
• Address Register
(AR}-
This 5-bit register
is
used to address the
18 internal registers. To gain access to any of the 18 registers, you
must first write the number of the register
(RO
through R17) to
be
modified into this register.
If
you write
an
address of 18 to
31,
no
register will be addressed.
• Horizontal Total Register
(RO}-
This 8-bit, write-only register sets
the time (number of characters) between the starting points of charac-
ter rows. This time, defined
in
character clock periods, includes
all
characters
in
a row, the delay before the horizontal sync pulse, the
width of the sync pulse, and the retrace time. Since the first character
is
zero (0), you must enter the number of character clock signals
you
want minus
1.
For instance, if you enter 112, there will be 113 character
positions between the start of any 2 consecutive rows. The default
value is
61
H or 97 decimal.
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