Page 5.3
Card/Circuit Description
Circuit Description
Function and Timing Decoding
PAL
U31,
PAL U32, and PAL U26 provide decoding for most of the com-
munication between the CPU, the CRTC,
and
the
RAM.
The inputs of
U31
and U32 are connected
to
the CPU's control
and
address busses.
U31
decodes the incoming
liD
addresses and
liD
operations from the
CPU
and
determines when one of the components
on
the card
is
being
addressed. Based on the address and the states of the control signals,
the
read
or write pulses are generated for the card.
U32
provides the system timing and decodes the video memory space.
The
NIDEO
output from this device
is
the character clock
and
has a
553
nanosecond period. This signal
is
used to control access to the display
RAM.
When this signal is low, the multiplexer connects the addresses
from
the 6845 to the
RAM.
When the
NIDEO
signal
is
high, the CPU
addresses are connected to the
RAM.
CRTC (6845) access time
is
308
nanoseconds and CPU access time
is
245 nanoseconds. When the
CPU
requests a memory access, U32 pulls the IOCHRDY
(liD
Channel Ready)
signal
to the wait state, and then synchronizes the CPU access of the
RAM
to
the correct time period. Because the CPU may not
be
done reading
the
data when the CRTC time slot occurs, the data
from
the
RAM
is
latched into octal D latch U34
by
the IDISCPU signal from U32.
The
timing
is
provided by oscillator
Y1
and
U32.
The output frequency
from
Y1
is
16.257 MHz. This signal
is
buffered by one NAND gate
in
U18.
The output from U18 drives the clock input to U32 and
is
supplied
to
the shift register which converts the data bytes into pixel data
(DOTCLK). Pins 13
(00)
and 14
(01)
of
U32
provide a divide by 8 function
for
video timing (character clock). Both of these outputs are at a frequency
of
2.0321
MHz, but the rising edge of 01
is
delayed 1 DOTCLK pulse
from
the rising edge of
00.
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