Page 5.8
Card/Circuit Description
Attribute Data Conversion
The
attribute
RAM
(U23)
is
addressed
in
parallel with
the
character
RAM.
The
byte contained
in
the attribute
RAM
then
is
decoded by PAL U25
into
IGATE and IINVERT signals. The intensity bit goes directly to latch
U30.
These three signals are delayed by two
NIDEO
pulses
by
U30.
The
first clock pulse latches these signals into the output of the latch
which
is
connected to three other inputs
in
the latch. The second clock
pulse
then sends these signals to the rest of the system. The IGATE
signal
is
used to block the video data. The IINVERT signal inverts the
video data. The intensity bit
is
buffered by two gates of U19 and then
passed through latch U15
in
the same manner
as
the video data. The
intensity bit
is
also buffered by U16 and filtered for
RFI
before being sent
to
the monitor on pin 6 of the output connector.
The
BLINK bit from the attribute
RAM
is
delayed by flip-flop U27 and
then
connected to U
13
which gates the intensity bit into
U15.
Sync
The
horizontal and vertical sync pulses are generated
by
the CRTC. The
horizontal sync
is
sent through U30, U
15,
and
U16 just like the video
data and connected to pin 8 of the output connector. The vertical sync
is
processed through the same chips
and
connected to the output connec-
tor at pin
9.
The vertical sync pulses are also divided
by
U11
to provide
the
CURCLK and BLKCLK signals into PAL U25.
6845CRTC
The
6845 CRT Controller provides the interface between the
CPU
and
a raster scan CRT display. All inputs and outputs are TTL compatible.
The
6845 functions as a group of programmable counters. Each counter
(register)
is
addressable by the CPU. These registers control
all
of the
functions necessary to control the video memory and the CRT display.
The
registers and their operation
is
described
in
Chapter
4,
"Software
Considerations."
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