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Zenith Data Systems Z-100 Series - Page 57

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Page 5.7
Card/Circuit Description
During its access time, the address from the CRTC
is
sent
to
the RAMs
through multiplexers U4, U21, and U22. Both the character RAM (U2)
and
the attribute RAM (U23) are addressed
in
parallel. The character data
output
is
latched into U3 by the
NIDEO
clock. Note that the RAM
is
ad-
dressed by the CRTC's character addresses
(RMAQ-RMA11)
only. The
data from the latch is used to address the character ROM (U5). Note
that the scan line addresses from the CRTC
(RAQ-RA3)
are connected
to
the character ROM but not to the RAM.
The character RAM is addressed by character location and the ASCII
data is latched into U3. This ASCII data and the scan line address from
the
CRTC address the ROM. This allows a different byte of pixel data
to
be
sent from the ROM each time the character is addressed. Because
of the way that the CRTC addresses the memory, the character RAM
is
addressed several times (once each scan line) until the character is
formed.
The output from the character ROM
is
latched into U8. U8
is
a universal
shift/storage register which is used as a parallel-in/ serial-out shift register.
U8
is described more fully at the end of this chapter, but only the parallel-in/
serial-out mode is used on this card. U8 is parallel-loaded by holding
the
S1
line high when the clock makes a low to high transition. This data
is
then clocked serially out of the
IC
by the DOTCLK. The data is gated
by
U13 and U14. U13 is a NAND gate which can be used to block the
video data. U14
is
an
exclusive OR gate. If the other input to U14 is
low,
the gate acts as a noninverting buffer. If the other input is high, the
gate acts as an inverting buffer. The data from U14 goes to the 1D input
of
U15
and
is
latched into the output by the DOTCLK. Jumper J3
is
used
to
select either the 1Q output or the 1Q* output from U15. The output
from
the jumper is then buffered by U16 (the upper 4 bits of U16 always
are
enabled by grounding G1).
The
output from the buffer is filtered by an
RFI
filter that is built into the
9-pin D connector and is then sent to pin 7 of the output connector.

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