Page 5.2
Card/Circuit Description
I/O
Decode---The I/O decode circuit receives the incoming address from
the
CPU and decides if any part of the card
is
being addressed. This
circuit enables the devices
on
the card which the
CPU
wishes to control.
Memory Decode---The memory decode circuit determines when the
RAM
on
the Z-329 Card
is
being addressed, converts the bus signals into the
correct logic for the RAM, and addresses the memory.
Timing
Generator-The
timing generator circuit controls arbitration of the
memory so that only the CPU or the CRTC can access the memory
at
any time. This circuit also provides the proper timing of the transfer of
data to and from RAM and to the video output.
CRTC-
The CRTC provides the sync pulses for the monitor and address
information to the RAMs during video cycles. The internal registers of
the
CRTC can be addressed to provide a number of functions.
Address
Mux-
The address mux (multiplexer) controls which device, the
CPU
or the CRTC,
is
in
control of addressing the
RAM.
Display
Memory-These
static RAMs are used to store the characters
which are to
be
displayed on the CRT and the associated attribute. The
standard memory devices are 2K x 8 but 8K x 8
ICs
can
be
installed.
Character
Generator-The
character generator
is
a
ROM.
This device
contains the font for the display memory. The data
in
the display memory
is
converted into pixel drive data by this device.
Video
Output-The
video output devices convert the parallel data from
the
character generator into serial data to drive a TTL input video monitor.
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