Zenith Data Systems Z-100 Series - Page 55

Page 5.5
Card/Circuit Description
CPU access to the RAM is less complicated, but requires that the CPU
wait for the correct time to access the
RAM. When the CPU wishes to
write to (or read from) the RAM, the IBUSREQ signal from
U31 places
the CPU in a WAIT state. When the access time arrives, the IRDY signal
from U32 cancels the WAIT. The address is allowed to connect to the
RAMs through the 3 multiplexers (U4, U21, and U22). Which of the two
RAMs is being addressed is determined by the AD line. The output enable
and write enable signals for the RAMs are generated by PAL U26. The
CPU data bus is separated from the RAM data busses by octal transceiv-
ers U2D and U24. The enabling and direction of these transceivers are
also controlled by signals from U26. The states of the transceivers are
shown
in Table 5.1. When a write function is done, U26 generates the
write logic to the selected RAM. When a read function
is performed, the
data
is latched into bus latch U34.
Table 5.1. Transceiver States
GAB STATE
Low
High
Low
GBASTATE
Low
High
High
OPERATION
Transfer data from B lines to A lines
Transfer data from A lines to B lines
Isolation (3-state)
Writing to the control register (U29) is straightforward. The 13BH signal
from U31 enables decoder U28. The truth table for decoder U28 is shown
in Table 5.2. Address lines AD, A 1, and A2 then select a low at the ad-
dressed output. This low causes the data
on the data bus to be latched
into control register U29.