Zynq ZedBoard User Manual

1-Aug-2012
20
2.6.2 Program Push Button Switch
A PROG push switch, BTN6, toggles EPP PROG_B. This initiates reconfiguring the PL-
subsection by the processor.
2.6.3 Processor Subsystem Reset
Power-on reset, labeled PS_RST/BTN7, erases all debug configurations. The external system
reset allows the user to reset all of the functional logic within the device without disturbing the
debug environment. For example, the previous break points set by the user remain valid after
system reset. Due to security concerns, system reset erases all memory content within the PS,
including the OCM. The PL is also reset in system reset. System reset does not re-sample the
boot mode strapping pins.
2.7 User I/O
2.7.1 User Push Buttons
The ZedBoard provides 7 user GPIO push buttons to the EPP; five on the PL-side and two on the
PS-side.
Pull-downs provide a known default state, pushing each button connects to Vcco.
Table 12 - Push Button Connections
Signal Name
Subsection
Zynq EPP pin
BTNU
PL
T18
BTNR
PL
R18
BTND
PL
R16
BTNC
PL
P16
BTNL
PL
N15
PB1
PS
D13 (MIO 50)
PB2
PS
C10 (MIO 51)
2.7.2 User DIP Switches
The ZedBoard has eight user dip switches, SW0-SW7, providing user input. SPDT switches
connect the I/O through a 10kΩ resistorto the VADJ voltage supply or GND.
Table 13 - DIP Switch Connections
Signal Name
Zynq EPP pin
SW0
F22
SW1
G22
SW2
H22
SW3
F21
SW4
H19
SW5
H18
SW6
H17
SW7
M15

Zynq ZedBoard Specifications

General

Processor	Dual-core ARM Cortex-A9
Clock Speed	667 MHz
System Memory	512 MB DDR3
Flash Memory	256 MB
Video Output	HDMI, VGA
Storage	SD Card Slot
FPGA	Xilinx Zynq-7000 XC7Z020
Ethernet	10/100/1000 Mbps Ethernet
USB	USB 2.0 (OTG and Host)
Audio	3.5mm jack, HDMI
Expansion Connectors	FMC, Pmod
Power	5V DC

Summary

Revision History

Introduction

Zynq Bank Pin Assignments

Overview of Zynq bank pin assignments and detailed I/O connections.

ZedBoard Overview

Description of the ZedBoard, its features, and capabilities.

Functional Description

EPP Details

Details about the Xilinx Zynq XC7Z020-1CSG484 EPP and silicon grades.

Memory Interfaces

Information on DDR3, SPI flash, and SD card interfaces for data storage.

USB Connectivity

Details on USB OTG, USB-to-UART bridge, and USB-JTAG interfaces.

Display and Audio Output

Information on HDMI output, VGA connector, and I2S audio codec.

Clock and Reset Sources

Details on clock sources and reset mechanisms for system control.

User Input/Output

Information on push buttons, DIP switches, and user LEDs for interaction.

Ethernet Interface

Details on the 10/100/1000 Ethernet PHY for network connectivity.

Expansion Headers

Information on LPC FMC, Pmod, and AMS connectors for extensibility.

Configuration Modes

Details on Zynq boot process and configuration options, including JTAG.

Power Management

Information on power input, regulators, sequencing, estimation, and probes.

Zynq EPP Banks

Zynq EPP Bank Voltages

Default voltage assignments for Zynq PS and PL banks.

Jumper Settings

Mechanical