Zynq ZedBoard User Manual

1-Aug-2012
35
4 Jumper Settings
Table 22 - Jumper Settings
Ref Designator
Description
Default Setting
Function
JP1
Microphone Input Bias
Open – No Electret
Microphone
Short to enable Bias
Voltage for Electret
Microphone. Right
Channel only.
JP2
Vbus 5V Enable
Open – 5V
Disconnected
Short to enable 5V
output to USB OTG
Connector, J13, for
either Host or OTG
modes.
JP3
USB Vbus Capacitor
Setting
Open – Device Mode
Short for Host mode
(>120uF).
Open for Device or
OTG modes (4.7uF).
JP4
CFGBVS Select
Open
Pre-configuration I/O
standard type for the
dedicated
configuration bank 0.
Open sets bank0
voltage to 1.8V
JP5
PUDC Select
Open
Active Low input
enables internal pull-
ups during
configuration on
all SelectIO pins.
JP6
PS_MIO0 Pull-Down
Short
Install for SD Card
boot on CES silicon.
See Zynq Errata.
JP7
Boot_Mode[3]/MIO[2]
GND – Cascaded
JTAG
JTAG Mode. GND
cascades PS and PL
JTAG chains. VCC
makes JTAG chains
independent.
JP8
JP9
JP10
Boot_Mode[0]/MIO[3]
Boot_Mode[1]/MIO[4]
Boot_Mode[2]/MIO[5]
110 – SD Card
Boot Device Select
See Zynq
Configuration Modes
JP11
Boot_Mode[4]/MIO[6]
GND – PLL Used
PLL Select. GND
uses PS PLLs. VCC
bypasses internal PS
PLLs
JP12
XADC Ferrite Bead
Disable
Open
Short bypasses
XADC-GND ferrite
bead connection to
board GND.
JP13
JTAG PS-RST
Open
Short connects JTAG
PROG-RST to PS
Reset.
J18
Vadj Select
1.8V
Selects Vadj (1.8V,
2.5V, or 3.3V)

Zynq ZedBoard Specifications

General

Processor	Dual-core ARM Cortex-A9
Clock Speed	667 MHz
System Memory	512 MB DDR3
Flash Memory	256 MB
Video Output	HDMI, VGA
Storage	SD Card Slot
FPGA	Xilinx Zynq-7000 XC7Z020
Ethernet	10/100/1000 Mbps Ethernet
USB	USB 2.0 (OTG and Host)
Audio	3.5mm jack, HDMI
Expansion Connectors	FMC, Pmod
Power	5V DC