1-Aug-2012
2.9.2 Digilent Pmod™ Compatible Headers (2x6)
The ZedBoard has five Digilent Pmod™ compatible headers (2x6). These are right-angle, 0.1”
female headers that include eight user I/O plus 3.3V and ground signals as show in the figure
below.
Four Pmod connectors interface to the PL-side of the EPP. These will connect to EPP Bank 13
(3.3V). One Pmod, JE1, connects to the PS-side of the EPP on MIO pins [7,9-15] in EPP MIO
Bank 0/500 (3.3V). Uses for this Pmod include PJTAG access (MIO[10-13]) as well as nine other
hardened MIO peripherals (SPI, GPIO, CAN, I2C, UART, SD, QSPI, Trace, Watchdog).
The four PL Pmod connectors are placed in adjacent pairs on the board edge such that the
clearance between Pin 6 of header #1 and Pin 1 of header #2 is 10mm.
Two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed
differentially to support LVDS running at 525Mbs.
All Pmod data lines, 8 per connector, are protected with two 4-channel TE SESD1004Q4UG-
0020-090.
FPGA I/O
3.3V
1
2
3
4
5
6
FPGA I/O
FPGA I/O
FPGA I/O
7
8
9
10
11
12
FPGA I/O
3.3V
FPGA I/O
FPGA I/O
FPGA I/O
Figure 12 - Pmod Connections
A couple links to Pmod examples are provided:
http://www.em.avnet.com/en-us/design/drc/Pages/Digilent-PmodWiFi-802-11bgn-
WiFi-Interface.aspx
http://www.em.avnet.com/en-us/design/drc/Pages/Digilent-Pmod-RS232-Serial-
Converter-and-Interface.aspx
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