Zynq ZedBoard User Manual

1-Aug-2012
9
2.2.2 SPI Flash
The ZedBoard features a 4-bit SPI (quad-SPI) serial NOR flash. The Spansion S25FL256S is
used on this board. The Multi-I/O SPI Flash memory is used to provide non-volatile code, and
data storage. It can be used to initialize the PS subsystem as well as configure the PL
subsystem (bitstream). Spansion provides Spansion Flash File System (FFS) for use after
booting the Zynq EPP.
The relevant device attributes are:
 256Mbit
 x1, x2, and x4 support
 Speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz
o In Quad-SPI mode, this translates to 400Mbs
 Powered from 3.3V
The SPI Flash connects to the EPP supporting up to Quad-I/O SPI interface. This requires
connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq
datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is connected to a
20K pull-up resistor to 3.3V. This allows a QSPI clock frequency greater than FQSPICLK2.
Note: Zynq only supports 24-bit addressing, however the full capacity of the 256Mb Flash can be
accessed via internal bank switching. As of now the S25FL256S is not supported in iMPACT.
Note: 14.x is required for in-direct QSPI Flash Programming.
Table 3 – QSPI Flash Pin Assignment and Definitions
Signal Name
Description
Zynq EPP Pin
QSPI Pin
DQ0
Data0
A2 (Bank MIO0/500)
5
DQ1
Data1
F6 (MIO Bank 0/500)
2
DQ2
Data2
E4 (MIO Bank 0/500)
3
DQ3
Data3
A3 (MIO Bank 0/500)
7
SCK
Serial Data Clock
A4 (MIO Bank 0/500)
6
CS
Chip Select
A1 (MIO Bank 0/500)
1
FB Clock
QSPI Feedback
E5 (MIO Bank 0/500)
N/C
Note: The QSPI data and clock pins are shared with the Boot Mode jumpers.

Zynq ZedBoard Specifications

General

Processor	Dual-core ARM Cortex-A9
Clock Speed	667 MHz
System Memory	512 MB DDR3
Flash Memory	256 MB
Video Output	HDMI, VGA
Storage	SD Card Slot
FPGA	Xilinx Zynq-7000 XC7Z020
Ethernet	10/100/1000 Mbps Ethernet
USB	USB 2.0 (OTG and Host)
Audio	3.5mm jack, HDMI
Expansion Connectors	FMC, Pmod
Power	5V DC