Zynq ZedBoard User Manual

1-Aug-2012
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2.10 Configuration Modes
Zynq-7000 EPP devices use a multi-stage boot process that supports both non-secure and
secure boot (note that secure boot is not supported for CES silicon.) The PS is the master of the
boot and configuration process. The following table shows the Zynq configuration modes. Upon
reset, the device mode pins are read to determine the primary boot device to be used: NOR,
NAND, Quad-SPI, SD Card or JTAG.
By default, the ZedBoard uses the SD Card configuration mode. The boot mode pins are
MIO[8:2] and are used as follows:
 MIO[2]/Boot_Mode[3] sets the JTAG mode
 MIO[5:3]/Boot_Mode[2:0] select the boot mode
 MIO[6]/Boot_Mode[4] enables the internal PLL
 MIO[8:7]/Vmode[1:0] are used to configure the I/O bank voltages, however these are
fixed on ZedBoard and not configurable
The ZedBoard provides jumpers for MIO[6:2]. These are 1x3 jumpers connected as shown
below. All mode pins can be pulled high or low through a 20 KΩ resistor.
Figure 15 - Configuration Mode Jumpers
These jumpers allow users to change the mode options, including using cascaded JTAG
configuration as well as using the internal PLL.
As noted above, the VMODE pins are strapped permanently to set Bank 500 and 501 voltages to
3.3V and 1.8V. These are not jumper selectable.

Zynq ZedBoard Specifications

General

Processor	Dual-core ARM Cortex-A9
Clock Speed	667 MHz
System Memory	512 MB DDR3
Flash Memory	256 MB
Video Output	HDMI, VGA
Storage	SD Card Slot
FPGA	Xilinx Zynq-7000 XC7Z020
Ethernet	10/100/1000 Mbps Ethernet
USB	USB 2.0 (OTG and Host)
Audio	3.5mm jack, HDMI
Expansion Connectors	FMC, Pmod
Power	5V DC

Summary

Revision History

Introduction

Zynq Bank Pin Assignments

Overview of Zynq bank pin assignments and detailed I/O connections.

ZedBoard Overview

Description of the ZedBoard, its features, and capabilities.

Functional Description

EPP Details

Details about the Xilinx Zynq XC7Z020-1CSG484 EPP and silicon grades.

Memory Interfaces

Information on DDR3, SPI flash, and SD card interfaces for data storage.

USB Connectivity

Details on USB OTG, USB-to-UART bridge, and USB-JTAG interfaces.

Display and Audio Output

Information on HDMI output, VGA connector, and I2S audio codec.

Clock and Reset Sources

Details on clock sources and reset mechanisms for system control.

User Input/Output

Information on push buttons, DIP switches, and user LEDs for interaction.

Ethernet Interface

Details on the 10/100/1000 Ethernet PHY for network connectivity.

Expansion Headers

Information on LPC FMC, Pmod, and AMS connectors for extensibility.

Configuration Modes

Details on Zynq boot process and configuration options, including JTAG.

Power Management

Information on power input, regulators, sequencing, estimation, and probes.

Zynq EPP Banks

Zynq EPP Bank Voltages

Default voltage assignments for Zynq PS and PL banks.

Jumper Settings

Mechanical