Zynq ZedBoard User Manual

1-Aug-2012
26
Table 17 - Analog Header Pin Out
Name
Description
Requirement
XADC
Header
EPP Pin
V
P
/V
N
Two pins required. Dedicated
pins on the 7 series package.
This is the dedicated analog
input channel for the ADC(s).
1V peak-to-
peak input
maximum
1
2
XADC-VN-R : M12
XADC-VP-R : L11
V
AUX0P
/V
AUX0N
Two pins required. Auxiliary
analog input channel 0. Two
dedicated channels needed for
simultaneous sampling
applications. Should also
support use as IO inputs by
disconnection of anti-alias cap
see
1V peak-to-
peak input
maximum
6
3
XADC-AD0N-R : E16
XADC-AD0P-R : F16
V
AUX8P
/V
AUX8N
Two pins required. Auxiliary
analog input channel 8. Two
dedicated channels needed for
simultaneous sampling
applications. Should also
support use as IO inputs by
disconnection of anti-alias cap
see
1V peak-to-
peak input
maximum
7
8
XADC-AD8N-R : D17
XADC-AD8P-R : D16
DXP/DXN
Two pins required. Access to
thermal Diode
12
9
XADC-DXN : N12
XADC-DXP : N11
AGND
Three pins required. Analog
ground reference GNDADC.
Analog channel isolation
4
5
10
VCCADC
One pin. This is the analog 1.8V
supply for XADC.
1.8V ±5%
@150mA max
14
V
REF
One pin. This is the 1.25V
reference from the board.
1.25V ±0.2%
50ppm/ºC
@5mA max
11
AV_5V
Filtered 5V supply from board.
5V ±5%
@150mA max
13
GPIO
General Purpose I/O
Voltage set by
Vadj
G0: 18
G1: 17
G2: 20
G3: 19
H15
R15
K15
J15
Vadj
Adjustable Voltage, set by J18
1.8V, 2.5V,
3.3V

Zynq ZedBoard Specifications

General

Processor	Dual-core ARM Cortex-A9
Clock Speed	667 MHz
System Memory	512 MB DDR3
Flash Memory	256 MB
Video Output	HDMI, VGA
Storage	SD Card Slot
FPGA	Xilinx Zynq-7000 XC7Z020
Ethernet	10/100/1000 Mbps Ethernet
USB	USB 2.0 (OTG and Host)
Audio	3.5mm jack, HDMI
Expansion Connectors	FMC, Pmod
Power	5V DC