Advantech PCA-6145B - DMA Channel Assignments; DMA Controller Registers

Appendix C Detailed system information 69
DMA channel assignments
Channel Function
0 Spare (8-bit transfer)
1 SDLC (8-bit transfer)
2 Floppy disk (8-bit transfer)
3 Spare (8-bit transfer)
4 Cascade for DMA controller 1
5 Spare (16-bit transfer)
6 Spare (16-bit transfer)
7 Spare (16-bit transfer)
DMA controller registers
Address Command code
0C0 CH0 base and current address
0C2 CH0 base and current word count
0C4 CH1 base and current address
0C6 CH1 base and current word count
0C8 CH2 base and current address
0CA CH2 base and current word count
0CC CH3 base and current address
0CE CH3 base and current word count
0D0 Read status register/Write command register
0D2 Write mode register
0D4 Read temporary register/Write command register
0D6 Write mode register
0D8 Clear byte pointer flip-flop
0DA Read status register/Write command register
0DC Write mode register
0DE Write all mask register bus