MIL-STD-1553 Reference Manual
13.2 Definition of Terms
Refers to software interface between the API S/W Library function calls
and the API Target S/W.
a system of memory addressing in which numbers that occupy more than
one byte in memory are stored “big end first” with the uppermost 8 bits
at the lowest address.
commands sent to multiple RTs at once. The RTs are responsible for
distinguishing between broadcast and non-broadcast command messages.
An RT address of 11111 (31) indicates a broadcast message.
information detailing the location of the data buffer(s) used for the LS
and HS transfer(s), and the status and event information associated with
the transfer. A buffer header is to be associated with the data buffer(s)
by the programmer for any transfer to/from the BC or RT
an ID number associated with the Buffer Header structure
an area of memory on the AIM device (global RAM) assigned by the
programmer to accommodate transfer(s) to/from the BC or RT
command used by the AIM Target s/w to control the Target device
indicates the AIM 1553 board supports two dual redundant MIL-STD-
1553 data stream
page oriented electrical erasable and programmable memory
a self-contained block of code with a specific purpose that returns a
single value.
file containing C++ code consisting of definitions which are used by the
executable code
the time between LS message transmissions with a minimum gap time,
as specified in MIL-STD-1553, of 4.0 microseconds
a signal from a device attached to a computer or from a program within
the computer that causes the main program that operates the computer
(the operating system) to stop and figure out what to do next
a system of memory addressing in which numbers that occupy more than
one byte in memory are stored “little end first” with the lowest 8 bits at
the lowest address.
sequence of minor frames defined for transfer (max 64 minor frames in a
major frame)
military specification defining a digital time division command/response
multiplexed databus
based on MIL-STD-1553B, augmented with requirements to support the
aircraft/store electrical interconnection system between aircraft and
stores (any external device attached to the aircraft (such as bombs,
missiles, etc.)
sequence of LS transfers (max 128 transfers defined in a minor frame)
Unique five bit codes that are sent to specific RTs to check their status,
control their operation and manage the bus.
Monitor Status
Trigger pattern
8 bits in the Monitor Status Word that reflect the results of the Monitor
Trigger Block execution of the BIU Processor.
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