AT90S2313
23
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this
pulse, the delay timer starts counting the Time-out period t
TOUT
. Refer to page 36 for details on operation of the Watchdog.
Figure 27. Watchdog Reset During Operation
Interrupt Handling
The AT90S2313 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK -
Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft-
ware can set (one) the I-bit to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI - is
executed.
For Interrupts triggered by events that can remain static (e.g. the Output Compare register1 matching the value of
Timer/Counter1) the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition
persists, the flag will not be set until the event occurs the next time.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,
hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by
writing a logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set
and remembered until the interrupt is enabled, or the flag is cleared by software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is
active.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
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