AT90S2313
37
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Bit 3 - WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function
is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following
procedure must be followed:
1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though
it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.
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Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The
different prescaling values and their corresponding timeout periods are shown in Table 14.
Note: The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section.
The WDR - Watchdog Reset - instruction should always be executed before the Watchdog Timer is enabled. This ensures that
the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without
reset, the watchdog timer may not start counting from zero.
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4ms, depending on the V
CC
voltages. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-
caution must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on power-up/down. This causes
the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU
operation under these conditions may cause the program counter to perform unintentional jumps and eventually execute
the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in
this case.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of
the EEPROM Control Register for details on this.
When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed.
Table 14. Watch Dog Timer Prescale Select
WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles
Typical time-out
at VCC = 3.0V
Typical time-out
at VCC = 5.0V
0 0 0 16K cycles 47 ms 15 ms
0 0 1 32K cycles 94 ms 30 ms
0 1 0 64K cycles 0.19 s 60 ms
0 1 1 128K cycles 0.38 s 0.12 s
1 0 0 256K cycles 0.75 s 0,24 s
1 0 1 512K cycles 1.5 s 0.49 s
1 1 0 1,024K cycles 3.0 s 0.97 s
1 1 1 2,048K cycles 6.0 s 1.9 s
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