AT90S2313
36
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $0000. Timer Overflow Interrupt1
operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer Overflow
Interrupt1 and global interrupts are enabled. This does also apply to the Timer Output Compare1 flag and interrupt.
Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1MHz This is the typical value at V
CC
= 5V.
See characterization data for typical values at other V
CC
levels. By controlling the Watchdog Timer prescaler, the Watchdog
reset interval can be adjusted, see Table 14 for a detailed description. The WDR - Watchdog Reset - instruction resets the
Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period
expires without another Watchdog reset, the AT90S2313 resets and executes from the reset vector. For timing details on
the Watchdog reset, refer to page 23.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is
disabled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 33. Watchdog Timer
Watchdog Timer Control Register - WDTCR
•
Bits 7..5 - Res: Reserved bits
These bits are reserved bits in the AT90S2313 and will always read as zero.
•
Bit 4 - WDTOE: Watchdog Turn-Off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
Table 13. PWM Outputs OCR = $0000 or TOP
COM1A1 COM1A0 OCR1A Output OC1
1 0 $0000 L
10TOP H
1 1 $0000 H
11TOP L
Bit 76543210
$21 ($41) - - - WDTOE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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