AT90S2313
35
Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1 - OCR1A, form a 8, 9 or 10-bit, free-
running, glitch-free and phase correct PWM with output on the PB3(OC1) pin. Timer/Counter1 acts as an up/down counter,
counting up from $0000 to TOP (see Table 11), where it turns and counts down again to zero before the cycle is repeated.
When the counter value matches the contents of the 8, 9 or 10 least significant bits of OCR1A, the PB3(OC1) pin is set or
cleared according to the settings of the COM1A1 and COM1A0 bits in the Timer/Counter1 Control Register TCCR1. Refer
to Table 12 for details.
Note that in the PWM mode, the 10 least significant OCR1A bits, when written, are transferred to a temporary location.
They are latched when Timer/Counter1 reaches TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in
the event of an unsynchronized OCR1A write. See Figure 32 for an example.
Figure 32. Effects on Unsynchronized OCR1 Latching
During the time between the write and the latch operation, a read from OCR1A will read the contents of the temporary
location. This means that the most recently written value always will read out of OCR1A.
When the OCR1 contains $0000 or TOP, the output OC1 is updated to low or high on the next compare match according to
the settings of COM1A1/COM1A0. This is shown in Table 13.
Table 11. Timer TOP Values and PWM Frequency
PWM Resolution Timer TOP Value Frequency
8-bit $00FF (255) f
TC1
/510
9-bit $01FF (511) f
TC1
/1022
10-bit $03FF(1023) f
TC1
/2046
Table 12. Compare1 Mode Select in PWM Mode
COM1A1 COM1A0 Effect on OC1
0 0 Not connected
0 1 Not connected
10
Cleared on compare match, upcounting. Set on compare match, downcounting (non-
inverted PWM).
11
Cleared on compare match, downcounting. Set on compare match, upcounting (inverted
PWM).
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alue changes
Compare Value changes
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