AT90S2313
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• TCNT1 Timer/Counter1 Read:
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the
high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU
receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit
register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1
is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset
with the written value.
Timer/Counter1 Output Compare Register A - OCR1AH and OCR1AL
The output compare register is a 16-bit read/write register.
The Timer/Counter1 Output Compare Register contains the data to be continuously compared with Timer/Counter1.
Actions on compare matches are specified in the Timer/Counter1 Control and Status register.
Since the Output Compare Register - OCR1A - is a 16-bit register, a temporary register TEMP is used when OCR1A is writ-
ten to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH, the data is
temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL, the TEMP register is simultaneously
written to OCR1AH. Consequently, the high byte OCR1AH must be written first for a full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform
access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts
are re-enabled.
Timer/Counter1 Input Capture Register - ICR1H and ICR1L
The input capture register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -
ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same
time, the input capture flag - ICF1 - is set (one).
Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to
ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and
the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the
CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit
register read operation.
The TEMP register is also used when accessing TCNT1 and OCR1A. If the main program and also interrupt routines
perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if
interrupts are re-enabled.
Bit 151413121110 9 8
$2B ($4B) MSB OCR1AH
$2A ($4A) LSB OCR1AL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
00000000
Bit 151413121110 9 8
$25 ($45) MSB ICR1H
$24 ($44) LSB ICR1L
76543210
Read/Write RRRRRRRR
RRRRRRRR
Initial value 0 0 0 0 0 0 0 0
00000000
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