AT90S2313
22
Figure 25. MCU Start-Up, RESET
Controlled Externally
External Reset
An external reset is generated by a low level on the RESET
pin. Reset pulses longer than 50 ns will generate a reset, even
if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage - V
RST
on its positive edge, the delay timer starts the MCU after the Time-out period t
TOUT
has
expired.
Figure 26. External Reset During Operation
VCC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
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