AT90S2313
26
External Interrupts
The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if
the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external
interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the
MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt
will trigger as long as the pin is held low.
The external interrupts are set up as described in the specification for the MCU Control Register - MCUCR.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the
interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this
4 clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2.
The vector is normally a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs
during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served
.
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes)
is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the
AVR
exits
from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is
served.
MCU Control Register - MCUCR
The MCU Control Register contains control bits for general MCU functions.
•
Bits 7, 6 - Res: Reserved bits
These bits are reserved bits in the AT90S2313 and always read as zero.
•
Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the
MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just
before the execution of the SLEEP instruction.
•
Bit 4 - SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.
When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph “Sleep Modes”
below.
•
Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 bit 1 and bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the
GIMSK register is set. The level and edges on the external INT1 pin that activate the interrupt are defined in the following
Table 5:
Note: When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register.
Otherwise an interrupt can occur when the bits are changed.
Bit 76543210
$35 ($55) - - SE SM ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 5. Interrupt 1 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
01Reserved
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.
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