Atmel ATmega8535L

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300

ATmega8535(L)

2502K–AVR–10/06

Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC.

2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register 181

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

Main Page

Features1
Pin Configurations2
- Disclaimer2
Overview3
- Block Diagram3
- AT90S8535 Compatibility4
  - AT90S8535 Compatibility Mode4
- Pin Descriptions5
Resources6
About Code Examples7
AVR CPU Core8
- Introduction8
- Architectural Overview8
- ALU - Arithmetic Logic Unit9
- Status Register10
- General Purpose Register File11
  - The X-register, Y-register, and Z-register12
- Stack Pointer12
- Instruction Execution Timing13
- Reset and Interrupt Handling13
  - Interrupt Response Time15
AVR ATmega8535 Memories16
- In-System Reprogrammable Flash Program Memory16
- SRAM Data Memory17
  - Data Memory Access Times18
- EEPROM Data Memory18
- I/O Memory23
System Clock and Clock Options24
- Clock Systems and their Distribution24
- Clock Sources25
- Default Clock Source25
- Crystal Oscillator25
- Low-frequency Crystal Oscillator28
- External RC Oscillator28
- Calibrated Internal RC Oscillator29
  - Oscillator Calibration Register - OSCCAL30
- External Clock31
- Timer/Counter Oscillator31
Power Management and Sleep Modes32
- MCU Control Register - MCUCR32
- Idle Mode33
- ADC Noise Reduction Mode33
- Power-down Mode33
- Power-save Mode33
- Standby Mode34
- Extended Standby Mode34
- Minimizing Power Consumption35
System Control and Reset36
- Resetting the AVR36
- Reset Sources36
- Power-on Reset38
- External Reset39
- Brown-out Detection39
- Watchdog Reset40
- MCU Control and Status Register - MCUCSR40
- Internal Voltage Reference41
  - Voltage Reference Enable Signals and Start-up Time41
- Watchdog Timer41
  - Watchdog Timer Control Register - WDTCR42
- Timed Sequences for Changing the Configuration of the Watchdog Timer45
Interrupts46
- Interrupt Vectors in ATmega853546
  - Moving Interrupts Between Application and Boot Space49
  - General Interrupt Control Register - GICR49
I/O-Ports51
- Introduction51
- Ports as General Digital I/O52
- Alternate Port Functions57
- Register Description for I/O-Ports66
External Interrupts68
- MCU Control Register - MCUCR68
- MCU Control and Status Register - MCUCSR69
- General Interrupt Control Register - GICR69
- General Interrupt Flag Register - GIFR70
8-bit Timer/Counter0 with PWM71
- Overview71
  - Registers71
  - Definitions72
- Timer/Counter Clock Sources72
- Counter Unit72
- Output Compare Unit73
- Compare Match Output Unit75
  - Compare Output Mode and Waveform Generation75
- Modes of Operation76
- Timer/Counter Timing Diagrams80
- 8-bit Timer/Counter Register Description83
Timer/Counter0 and Timer/Counter1 Prescalers87
- Internal Clock Source87
- Prescaler Reset87
- External Clock Source87
- Special Function IO Register - SFIOR88
16-bit Timer/Counter189
- Overview89
- Accessing 16-bit Registers92
  - Re-using the Temporary High Byte Register94
- Timer/Counter Clock Sources95
- Counter Unit95
- Input Capture Unit96
- Output Compare Units98
- Compare Match Output Unit100
  - Compare Output Mode and Waveform Generation100
- Modes of Operation101
- Timer/Counter Timing Diagrams108
- 16-bit Timer/Counter Register Description110
8-bit Timer/Counter2 with PWM and Asynchronous Operation117
- Overview117
  - Registers118
  - Definitions118
- Timer/Counter Clock Sources118
- Counter Unit119
- Output Compare Unit119
- Compare Match Output Unit121
  - Compare Output Mode and Waveform Generation121
- Modes of Operation122
- Timer/Counter Timing Diagrams126
- 8-bit Timer/Counter Register Description128
- Asynchronous Operation of the Timer/Counter131
- Timer/Counter Prescaler134
  - Special Function IO Register - SFIOR135
Serial Peripheral Interface - SPI136
- SS Pin Functionality141
- Data Modes144
USART145
- Overview145
  - AVR USART vs. AVR UART - Compatibility146
- Clock Generation146
- Frame Formats149
  - Parity Bit Calculation150
- USART Initialization150
- Data Transmission - The USART Transmitter152
- Data Reception - The USART Receiver155
- Asynchronous Data Reception158
- Multi-processor Communication Mode162
  - Using MPCM162
- Accessing UBRRH/UCSRC Registers163
  - Write Access163
  - Read Access164
- USART Register Description164
- Examples of Baud Rate Setting170
Two-wire Serial Interface174
- Features174
- Two-wire Serial Interface Bus Definition174
  - TWI Terminology174
  - Electrical Interconnection175
- Data Transfer and Frame Format175
- Multi-master Bus Systems, Arbitration and Synchronization177
- Overview of the TWI Module179
- TWI Register Description181
- Using the TWI185
- Transmission Modes188
- Multi-master Systems and Arbitration201
Analog Comparator203
- Special Function IO Register - SFIOR203
- Analog Comparator Control and Status Register - ACSR203
- Analog Comparator Multiplexed Input205
Analog-to-Digital Converter206
- Features206
- Operation207
- Starting a Conversion208
- Prescaling and Conversion Timing209
  - Differential Gain Channels212
- Changing Channel or Reference Selection212
  - ADC Input Channels213
  - ADC Voltage Reference213
- ADC Noise Canceler214
- ADC Conversion Result218
Boot Loader Support - Read-While-Write Self-Programming224
- Boot Loader Features224
- Application and Boot Loader Flash Sections224
  - Application Section224
  - BLS - Boot Loader Section224
- Read-While-Write and No Read-While-Write Flash Sections224
  - RWW - Read-While-Write Section225
  - NRWW - No Read-While-Write Section225
- Boot Loader Lock Bits226
- Entering the Boot Loader Program227
  - Store Program Memory Control Register - SPMCR228
- Addressing the Flash during Self- Programming229
- Self-Programming the Flash230
Memory Programming237
- Program And Data Memory Lock Bits237
- Fuse Bits238
  - Latching of Fuses239
- Signature Bytes239
- Calibration Byte239
- Parallel Programming Parameters, Pin Mapping, and Commands240
  - Signal Names240
- Parallel Programming242
- Serial Downloading251
Electrical Characteristics255
- Absolute Maximum Ratings*255
- DC Characteristics255
- External Clock Drive Waveforms258
- External Clock Drive258
- Two-wire Serial Interface Characteristics259
- SPI Timing Characteristics261
- ADC Characteristics263
ATmega8535 Typical Characteristics266
- Active Supply Current266
- Idle Supply Current270
- Power-Down Supply Current273
- Power-Save Supply Current274
- Standby Supply Current275
- Pin Pullup279
- Pin Driver Strength281
- Pin Thresholds And Hysteresis283
- BOD Thresholds And Analog Comparator Offset286
- Internal Oscillator Speed288
- Current Consumption Of Peripheral Units295
- Current Consumption In Reset And Reset Pulsewidth297
Register Summary299
Instruction Set Summary301
Ordering Information304
Packaging Information306
- 44A306
- 40P6307
- 44J308
- 44M1-A309
Errata310
- ATmega8535 Rev. A and B310
Datasheet Revision History311
- Changes from Rev. 2502J- 08/06 to Rev. 2502K- 10/06311
- Changes from Rev. 2502I- 06/06 to Rev. 2502J- 08/06311
- Changes from Rev. 2502H- 04/06 to Rev. 2502I- 06/06311
- Changes from Rev. 2502G- 04/05 to Rev. 2502H- 04/06311
- Changes from Rev. 2502F- 06/04 to Rev. 2502G- 04/05311
- Changes from Rev. 2502E-12/03 to Rev. 2502G-06/04311
- Changes from Rev. 2502E-12/03 to Rev. 2502F-06/04311
- Changes from Rev. 2502D-09/03 to Rev. 2502E-12/03311
- Changes from Rev. 2502C-04/03 to Rev. 2502D-09/03312
- Changes from Rev. 2502B-09/02 to Rev. 2502C-04/03312
- Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02313
Table of Contents315

Atmel ATmega8535L - Page 300

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