178
7679H–CAN–08/08
AT90CAN32/64/128
Figure 17-1. USARTn Block Diagram
(1)
Note: 1. Refer to Figure 1-2 on page 5 or Figure 1-3 on page 6, Table 9-15 on page 83, and Table 9-10
on page 79 for USARTn pin placement.
The dashed boxes in the block diagram separate the three main parts of the USARTn (listed
from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all
units. The Clock Generation logic consists of synchronization logic for external clock input used
by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USARTn module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
PARITY
GENERATOR
UBRRn[H:L]
UDRn (Transmit)
UCSRAn UCSRBn UCSRCn
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxDn
TxDn
PIN
CONTROL
UDRn (Receive)
PIN
CONTROL
XCKn
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA BUS
CLKio
SYNC LOGIC
Clock Generator
Transmitter
Receiver
To Next Page
Loading...
Need help?
General
